diff for duplicates of <566A2CB7.4050801@rock-chips.com> diff --git a/a/1.txt b/N1/1.txt index 1d217ad..54eb0dc 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -6,7 +6,7 @@ On 2015-12-10 8:32, Heiko Stuebner wrote: > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >> Initial release for rk3228 shared dtsi. >> ->> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> --- >> >> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ @@ -95,7 +95,7 @@ unlucky, that doesn't work...and our 3.10 kernel is using psci for rk3228's smp ops, maybe i should check that too, but i know nothing about psci for now :( >> + ->> + cpu0: cpu@f00 { +>> + cpu0: cpu at f00 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf00>; @@ -108,21 +108,21 @@ about psci for now :( >> + clocks = <&cru ARMCLK>; >> + }; >> + ->> + cpu1: cpu@f01 { +>> + cpu1: cpu at f01 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf01>; >> + resets = <&cru SRST_CORE1>; >> + }; >> + ->> + cpu2: cpu@f02 { +>> + cpu2: cpu at f02 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf02>; >> + resets = <&cru SRST_CORE2>; >> + }; >> + ->> + cpu3: cpu@f03 { +>> + cpu3: cpu at f03 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a7"; >> + reg = <0xf03>; @@ -136,7 +136,7 @@ about psci for now :( >> + #size-cells = <1>; >> + ranges; >> + ->> + pdma: pdma@110f0000 { +>> + pdma: pdma at 110f0000 { >> + compatible = "arm,pl330", "arm,primecell"; >> + reg = <0x110f0000 0x4000>; >> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -210,7 +210,7 @@ you're right, done. >> + #clock-cells = <0>; >> + }; >> + ->> + cru: clock-controller@110e0000 { +>> + cru: clock-controller at 110e0000 { >> + compatible = "rockchip,rk3228-cru"; >> + reg = <0x110e0000 0x1000>; >> + rockchip,grf = <&grf>; @@ -220,7 +220,7 @@ you're right, done. >> + assigned-clock-rates = <594000000>; >> + }; >> + ->> + gic: interrupt-controller@32010000 { +>> + gic: interrupt-controller at 32010000 { > please order by register address, so gic should move quite > a bit lower. done. @@ -236,12 +236,12 @@ done. > >> + }; >> + ->> + grf: syscon@11000000 { +>> + grf: syscon at 11000000 { >> + compatible = "syscon"; >> + reg = <0x11000000 0x1000>; >> + }; >> + ->> + timer: timer@110c0000 { +>> + timer: timer at 110c0000 { >> + compatible = "rockchip,rk3288-timer"; >> + reg = <0x110c0000 0x20>; >> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -249,7 +249,7 @@ done. >> + clock-names = "timer", "pclk"; >> + }; >> + ->> + emmc: dwmmc@30020000 { +>> + emmc: dwmmc at 30020000 { >> + compatible = "rockchip,rk3288-dw-mshc"; >> + clock-frequency = <37500000>; >> + clock-freq-min-max = <400000 37500000>; @@ -277,7 +277,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + pwm0: pwm@110b0000 { +>> + pwm0: pwm at 110b0000 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0000 0x10>; >> + #pwm-cells = <3>; @@ -288,7 +288,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + pwm1: pwm@110b0010 { +>> + pwm1: pwm at 110b0010 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0010 0x10>; >> + #pwm-cells = <3>; @@ -299,7 +299,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + pwm2: pwm@110b0020 { +>> + pwm2: pwm at 110b0020 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0020 0x10>; >> + #pwm-cells = <3>; @@ -310,7 +310,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + pwm3: pwm@110b0030 { +>> + pwm3: pwm at 110b0030 { >> + compatible = "rockchip,rk3288-pwm"; >> + reg = <0x110b0030 0x10>; >> + #pwm-cells = <2>; @@ -321,7 +321,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + uart0: serial@11010000 { +>> + uart0: serial at 11010000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11010000 0x100>; >> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -335,7 +335,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + uart1: serial@11020000 { +>> + uart1: serial at 11020000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11020000 0x100>; >> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -349,7 +349,7 @@ done. >> + status = "disabled"; >> + }; >> + ->> + uart2: serial@11030000 { +>> + uart2: serial at 11030000 { >> + compatible = "snps,dw-apb-uart"; >> + reg = <0x11030000 0x100>; >> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -371,7 +371,7 @@ done. >> + #size-cells = <1>; >> + ranges; >> + ->> + gpio0: gpio0@11110000 { +>> + gpio0: gpio0 at 11110000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11110000 0x100>; >> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -384,7 +384,7 @@ done. >> + #interrupt-cells = <2>; >> + }; >> + ->> + gpio1: gpio1@11120000 { +>> + gpio1: gpio1 at 11120000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11120000 0x100>; >> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -397,7 +397,7 @@ done. >> + #interrupt-cells = <2>; >> + }; >> + ->> + gpio2: gpio2@11130000 { +>> + gpio2: gpio2 at 11130000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11130000 0x100>; >> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -410,7 +410,7 @@ done. >> + #interrupt-cells = <2>; >> + }; >> + ->> + gpio3: gpio3@11140000 { +>> + gpio3: gpio3 at 11140000 { >> + compatible = "rockchip,gpio-bank"; >> + reg = <0x11140000 0x100>; >> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -528,9 +528,3 @@ done. >> +}; >> > - - --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 5b895da..1fa5386 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,10 @@ "ref\01449651853-1667-1-git-send-email-jeffy.chen@rock-chips.com\0" "ref\01449651853-1667-8-git-send-email-jeffy.chen@rock-chips.com\0" "ref\024573164.okRNXjvZ1B@phil\0" - "From\0Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" - "Subject\0Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi\0" + "From\0jeffy.chen@rock-chips.com (Jeffy Chen)\0" + "Subject\0[PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi\0" "Date\0Fri, 11 Dec 2015 09:53:59 +0800\0" - "To\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" - "Cc\0linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org" - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> - Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> - " Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Heiko,\n" @@ -25,7 +15,7 @@ "> Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen:\n" ">> Initial release for rk3228 shared dtsi.\n" ">>\n" - ">> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + ">> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>\n" ">> ---\n" ">>\n" ">> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++\n" @@ -114,7 +104,7 @@ "rk3228's smp ops, maybe i should check that too, but i know nothing \n" "about psci for now :(\n" ">> +\n" - ">> +\t\tcpu0: cpu@f00 {\n" + ">> +\t\tcpu0: cpu at f00 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\treg = <0xf00>;\n" @@ -127,21 +117,21 @@ ">> +\t\t\tclocks = <&cru ARMCLK>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu1: cpu@f01 {\n" + ">> +\t\tcpu1: cpu at f01 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\treg = <0xf01>;\n" ">> +\t\t\tresets = <&cru SRST_CORE1>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu2: cpu@f02 {\n" + ">> +\t\tcpu2: cpu at f02 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\treg = <0xf02>;\n" ">> +\t\t\tresets = <&cru SRST_CORE2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu3: cpu@f03 {\n" + ">> +\t\tcpu3: cpu at f03 {\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\tcompatible = \"arm,cortex-a7\";\n" ">> +\t\t\treg = <0xf03>;\n" @@ -155,7 +145,7 @@ ">> +\t\t#size-cells = <1>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tpdma: pdma@110f0000 {\n" + ">> +\t\tpdma: pdma at 110f0000 {\n" ">> +\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" ">> +\t\t\treg = <0x110f0000 0x4000>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -229,7 +219,7 @@ ">> +\t\t#clock-cells = <0>;\n" ">> +\t};\n" ">> +\n" - ">> +\tcru: clock-controller@110e0000 {\n" + ">> +\tcru: clock-controller at 110e0000 {\n" ">> +\t\tcompatible = \"rockchip,rk3228-cru\";\n" ">> +\t\treg = <0x110e0000 0x1000>;\n" ">> +\t\trockchip,grf = <&grf>;\n" @@ -239,7 +229,7 @@ ">> +\t\tassigned-clock-rates = <594000000>;\n" ">> +\t};\n" ">> +\n" - ">> +\tgic: interrupt-controller@32010000 {\n" + ">> +\tgic: interrupt-controller at 32010000 {\n" "> please order by register address, so gic should move quite\n" "> a bit lower.\n" "done.\n" @@ -255,12 +245,12 @@ ">\n" ">> +\t};\n" ">> +\n" - ">> +\tgrf: syscon@11000000 {\n" + ">> +\tgrf: syscon at 11000000 {\n" ">> +\t\tcompatible = \"syscon\";\n" ">> +\t\treg = <0x11000000 0x1000>;\n" ">> +\t};\n" ">> +\n" - ">> +\ttimer: timer@110c0000 {\n" + ">> +\ttimer: timer at 110c0000 {\n" ">> +\t\tcompatible = \"rockchip,rk3288-timer\";\n" ">> +\t\treg = <0x110c0000 0x20>;\n" ">> +\t\tinterrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -268,7 +258,7 @@ ">> +\t\tclock-names = \"timer\", \"pclk\";\n" ">> +\t};\n" ">> +\n" - ">> +\temmc: dwmmc@30020000 {\n" + ">> +\temmc: dwmmc at 30020000 {\n" ">> +\t\tcompatible = \"rockchip,rk3288-dw-mshc\";\n" ">> +\t\tclock-frequency = <37500000>;\n" ">> +\t\tclock-freq-min-max = <400000 37500000>;\n" @@ -296,7 +286,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tpwm0: pwm@110b0000 {\n" + ">> +\tpwm0: pwm at 110b0000 {\n" ">> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" ">> +\t\treg = <0x110b0000 0x10>;\n" ">> +\t\t#pwm-cells = <3>;\n" @@ -307,7 +297,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tpwm1: pwm@110b0010 {\n" + ">> +\tpwm1: pwm at 110b0010 {\n" ">> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" ">> +\t\treg = <0x110b0010 0x10>;\n" ">> +\t\t#pwm-cells = <3>;\n" @@ -318,7 +308,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tpwm2: pwm@110b0020 {\n" + ">> +\tpwm2: pwm at 110b0020 {\n" ">> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" ">> +\t\treg = <0x110b0020 0x10>;\n" ">> +\t\t#pwm-cells = <3>;\n" @@ -329,7 +319,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tpwm3: pwm@110b0030 {\n" + ">> +\tpwm3: pwm at 110b0030 {\n" ">> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" ">> +\t\treg = <0x110b0030 0x10>;\n" ">> +\t\t#pwm-cells = <2>;\n" @@ -340,7 +330,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tuart0: serial@11010000 {\n" + ">> +\tuart0: serial at 11010000 {\n" ">> +\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\treg = <0x11010000 0x100>;\n" ">> +\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -354,7 +344,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tuart1: serial@11020000 {\n" + ">> +\tuart1: serial at 11020000 {\n" ">> +\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\treg = <0x11020000 0x100>;\n" ">> +\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -368,7 +358,7 @@ ">> +\t\tstatus = \"disabled\";\n" ">> +\t};\n" ">> +\n" - ">> +\tuart2: serial@11030000 {\n" + ">> +\tuart2: serial at 11030000 {\n" ">> +\t\tcompatible = \"snps,dw-apb-uart\";\n" ">> +\t\treg = <0x11030000 0x100>;\n" ">> +\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -390,7 +380,7 @@ ">> +\t\t#size-cells = <1>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tgpio0: gpio0@11110000 {\n" + ">> +\t\tgpio0: gpio0 at 11110000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x11110000 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -403,7 +393,7 @@ ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgpio1: gpio1@11120000 {\n" + ">> +\t\tgpio1: gpio1 at 11120000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x11120000 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -416,7 +406,7 @@ ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgpio2: gpio2@11130000 {\n" + ">> +\t\tgpio2: gpio2 at 11130000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x11130000 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -429,7 +419,7 @@ ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tgpio3: gpio3@11140000 {\n" + ">> +\t\tgpio3: gpio3 at 11140000 {\n" ">> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" ">> +\t\t\treg = <0x11140000 0x100>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -546,12 +536,6 @@ ">> +\t};\n" ">> +};\n" ">>\n" - ">\n" - "\n" - "\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + > -e10aacc1de2ff196543082ff22bf677c5828b0bd26cb0285b3daf7455fb6108d +437770908358c63af2a1638b94cf910896571745da1865f8724e5bbabcfd9895
diff --git a/a/1.txt b/N2/1.txt index 1d217ad..36ecf63 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -6,7 +6,7 @@ On 2015-12-10 8:32, Heiko Stuebner wrote: > Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen: >> Initial release for rk3228 shared dtsi. >> ->> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> >> --- >> >> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++ @@ -528,9 +528,3 @@ done. >> +}; >> > - - --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 5b895da..965d711 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,20 +1,20 @@ "ref\01449651853-1667-1-git-send-email-jeffy.chen@rock-chips.com\0" "ref\01449651853-1667-8-git-send-email-jeffy.chen@rock-chips.com\0" "ref\024573164.okRNXjvZ1B@phil\0" - "From\0Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" + "From\0Jeffy Chen <jeffy.chen@rock-chips.com>\0" "Subject\0Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi\0" "Date\0Fri, 11 Dec 2015 09:53:59 +0800\0" - "To\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" - "Cc\0linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org" - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> - Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> - " Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>\0" + "To\0Heiko Stuebner <heiko@sntech.de>\0" + "Cc\0linux@arm.linux.org.uk" + linux-arm-kernel@lists.infradead.org + linux-rockchip@lists.infradead.org + linux-kernel@vger.kernel.org + devicetree@vger.kernel.org + Kumar Gala <galak@codeaurora.org> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + " Mark Rutland <mark.rutland@arm.com>\0" "\00:1\0" "b\0" "Hi Heiko,\n" @@ -25,7 +25,7 @@ "> Am Mittwoch, 9. Dezember 2015, 17:04:12 schrieb Jeffy Chen:\n" ">> Initial release for rk3228 shared dtsi.\n" ">>\n" - ">> Signed-off-by: Jeffy Chen <jeffy.chen-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + ">> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>\n" ">> ---\n" ">>\n" ">> arch/arm/boot/dts/rk3228.dtsi | 478 ++++++++++++++++++++++++++++++++++++++++++\n" @@ -546,12 +546,6 @@ ">> +\t};\n" ">> +};\n" ">>\n" - ">\n" - "\n" - "\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + > -e10aacc1de2ff196543082ff22bf677c5828b0bd26cb0285b3daf7455fb6108d +4f95a47ce0d5d95d5d6f683f47216dd9b31faaefb5da3b24ddd9195ec5dca746
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