diff for duplicates of <566B95FF.6090802@rock-chips.com> diff --git a/a/2.txt b/N1/2.txt index 3f63e27..0f97d9b 100644 --- a/a/2.txt +++ b/N1/2.txt @@ -1,4 +1,4 @@ ->From 390af4a7e1d35fd44b73124a397da90b6cdeb021 Mon Sep 17 00:00:00 2001 +From 390af4a7e1d35fd44b73124a397da90b6cdeb021 Mon Sep 17 00:00:00 2001 From: Caesar Wang <wxt@rock-chips.com> Date: Sat, 12 Dec 2015 11:24:20 +0800 Subject: [PATCH] clk: rockchip: include downstream muxes into fractional diff --git a/a/content_digest b/N1/content_digest index 48f0c9c..74169fd 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -303,7 +303,7 @@ "\01:2\0" "fn\00001-clk-rockchip-include-downstream-muxes-into-fractiona.patch\0" "b\0" - ">From 390af4a7e1d35fd44b73124a397da90b6cdeb021 Mon Sep 17 00:00:00 2001\n" + "From 390af4a7e1d35fd44b73124a397da90b6cdeb021 Mon Sep 17 00:00:00 2001\n" "From: Caesar Wang <wxt@rock-chips.com>\n" "Date: Sat, 12 Dec 2015 11:24:20 +0800\n" "Subject: [PATCH] clk: rockchip: include downstream muxes into fractional\n" @@ -517,4 +517,4 @@ "-- \n" 1.9.1 -c2f0f2544a02d4f2b01229eba5e9fcfc4830767f0356c1833010e64faec1d683 +6a6ae6f99501e6f404d7007f01e6287cc014f6a3dcc72f613de926ca489dd2ad
diff --git a/a/1.txt b/N2/1.txt index 8370d7e..d002515 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -10,7 +10,7 @@ I have fetch this series pacthes for my Kylin board. Anyway, I will send the patch for RK3036 if this patch has merged into mainline. -在 2015年08月22日 01:48, Heiko Stuebner 写道: +? 2015?08?22? 01:48, Heiko Stuebner ??: > Use the newly introduced possibility to combine the fractional dividers > with their downstream muxes for all fractional dividers on currently > supported Rockchip SoCs. @@ -285,4 +285,12 @@ mainline. -- -caesar wang | software engineer | wxt@rock-chip.com +caesar wang | software engineer | wxt at rock-chip.com + +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0001-clk-rockchip-include-downstream-muxes-into-fractiona.patch +Type: text/x-patch +Size: 9718 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151212/fb67e321/attachment.bin> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index 501ff88..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,6 +0,0 @@ -Content-Type: text/x-patch; - name="0001-clk-rockchip-include-downstream-muxes-into-fractiona.patch" -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename*0="0001-clk-rockchip-include-downstream-muxes-into-fractiona.pa"; - filename*1="tch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 3f63e27..0000000 --- a/a/2.txt +++ /dev/null @@ -1,213 +0,0 @@ ->From 390af4a7e1d35fd44b73124a397da90b6cdeb021 Mon Sep 17 00:00:00 2001 -From: Caesar Wang <wxt@rock-chips.com> -Date: Sat, 12 Dec 2015 11:24:20 +0800 -Subject: [PATCH] clk: rockchip: include downstream muxes into fractional - dividers - -Use the newly introduced possibility to combine the fractional dividers -with their downstream muxes for all fractional dividers on currently -supported RK3036 SoCs. - -Change-Id: I03ad115ddb007dc7d15acd5647d2bd1a81d6f884 -Signed-off-by: Caesar Wang <wxt@rock-chips.com> ---- - drivers/clk/rockchip/clk-rk3036.c | 60 ++++++++++++++++++++++++--------------- - 1 file changed, 37 insertions(+), 23 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c -index 77a9d75..5fb7171 100644 ---- a/drivers/clk/rockchip/clk-rk3036.c -+++ b/drivers/clk/rockchip/clk-rk3036.c -@@ -154,6 +154,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - * Clock-Architecture Diagram 1 - */ - -+ /* PD_CORE */ - GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED, - RK2928_CLKGATE_CON(0), 6, GFLAGS), - -@@ -161,6 +162,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - * Clock-Architecture Diagram 2 - */ - -+ /* PD_DDR */ - GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, - RK2928_CLKGATE_CON(0), 2, GFLAGS), - GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, -@@ -168,6 +170,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), - -+ /* PD_CORE */ - COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK2928_CLKGATE_CON(0), 7, GFLAGS), -@@ -175,6 +178,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK2928_CLKGATE_CON(0), 7, GFLAGS), - -+ /* PD_CPU (BUS) */ - GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS), - GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS), - COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0, -@@ -188,21 +192,25 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, - RK2928_CLKGATE_CON(0), 4, GFLAGS), - -+ /* PD_PERI */ - COMPOSITE(0, "aclk_peri_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS, - RK2928_CLKGATE_CON(2), 0, GFLAGS), - - GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0, - RK2928_CLKGATE_CON(2), 1, GFLAGS), -+ /* pclk_peri_src is soure for timers */ - DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), - GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0, - RK2928_CLKGATE_CON(2), 3, GFLAGS), -+ /* hclk_peri_src is soure for sclk_macref_out */ - DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO), - GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0, - RK2928_CLKGATE_CON(2), 2, GFLAGS), - -+ /* PD_TIMER */ - COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED, - RK2928_CLKSEL_CON(2), 4, 1, DFLAGS, - RK2928_CLKGATE_CON(1), 0, GFLAGS), -@@ -216,6 +224,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(2), 7, 1, DFLAGS, - RK2928_CLKGATE_CON(2), 5, GFLAGS), - -+ /* PD_UART */ - MUX(0, "uart_pll_clk", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, - RK2928_CLKSEL_CON(13), 10, 2, MFLAGS), - COMPOSITE_NOMUX(0, "uart0_src", "uart_pll_clk", 0, -@@ -227,22 +236,23 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0, - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 8, GFLAGS), -- COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, -+ COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(17), 0, -- RK2928_CLKGATE_CON(1), 9, GFLAGS), -- COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, -+ RK2928_CLKGATE_CON(1), 9, GFLAGS, -+ MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, -+ RK2928_CLKSEL_CON(13), 8, 2, MFLAGS)), -+ COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(18), 0, -- RK2928_CLKGATE_CON(1), 11, GFLAGS), -- COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, -+ RK2928_CLKGATE_CON(1), 11, GFLAGS, -+ MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, -+ RK2928_CLKSEL_CON(14), 8, 2, MFLAGS)), -+ COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(19), 0, -- RK2928_CLKGATE_CON(1), 13, GFLAGS), -- MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, -- RK2928_CLKSEL_CON(13), 8, 2, MFLAGS), -- MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, -- RK2928_CLKSEL_CON(14), 8, 2, MFLAGS), -- MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, -- RK2928_CLKSEL_CON(15), 8, 2, MFLAGS), -+ RK2928_CLKGATE_CON(1), 13, GFLAGS, -+ MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, -+ RK2928_CLKSEL_CON(15), 8, 2, MFLAGS)), - -+ /* PD_VIDEO */ - COMPOSITE(0, "aclk_vcodec", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK2928_CLKGATE_CON(3), 11, GFLAGS), -@@ -251,6 +261,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS, - RK2928_CLKGATE_CON(10), 6, GFLAGS), - -+ /* PD_VIO */ - COMPOSITE(0, "aclk_disp1_pre", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS, - RK2928_CLKGATE_CON(1), 4, GFLAGS), -@@ -261,6 +272,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS, - RK2928_CLKGATE_CON(3), 2, GFLAGS), - -+ /* MMC */ - COMPOSITE_NODIV(0, "sclk_sdmmc_src", mux_mmc_src_p, 0, - RK2928_CLKSEL_CON(12), 8, 2, DFLAGS, - RK2928_CLKGATE_CON(2), 11, GFLAGS), -@@ -286,28 +298,30 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK3036_EMMC_CON0, 1), - MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK3036_EMMC_CON1, 0), - -+ /* I2S */ - COMPOSITE(0, "i2s_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 9, GFLAGS), -- COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, -+ COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(7), 0, -- RK2928_CLKGATE_CON(0), 10, GFLAGS), -- MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, -- RK2928_CLKSEL_CON(3), 8, 2, MFLAGS), -+ RK2928_CLKGATE_CON(0), 10, GFLAGS, -+ MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, -+ RK2928_CLKSEL_CON(3), 8, 2, MFLAGS)), - COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0, - RK2928_CLKSEL_CON(3), 12, 1, MFLAGS, - RK2928_CLKGATE_CON(0), 13, GFLAGS), - GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT, - RK2928_CLKGATE_CON(0), 14, GFLAGS), - -+ /* SPDIF */ - COMPOSITE(0, "spdif_src", mux_pll_src_3plls_p, 0, - RK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS, - RK2928_CLKGATE_CON(2), 10, GFLAGS), -- COMPOSITE_FRAC(0, "spdif_frac", "spdif_src", 0, -+ COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0, - RK2928_CLKSEL_CON(9), 0, -- RK2928_CLKGATE_CON(2), 12, GFLAGS), -- MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, -- RK2928_CLKSEL_CON(5), 8, 2, MFLAGS), -+ RK2928_CLKGATE_CON(2), 12, GFLAGS, -+ MUX(SCLK_SPDIF, "sclk_spdif", mux_spdif_p, 0, -+ RK2928_CLKSEL_CON(5), 8, 2, MFLAGS)), - - GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED, - RK2928_CLKGATE_CON(1), 5, GFLAGS), -@@ -332,7 +346,6 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS), - MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(21), 3, 1, MFLAGS), -- - COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0, - RK2928_CLKSEL_CON(21), 9, 5, DFLAGS, - RK2928_CLKGATE_CON(2), 6, GFLAGS), -@@ -364,7 +377,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - GATE(HCLK_VIO_BUS, "hclk_vio_bus", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS), - GATE(HCLK_LCDC, "hclk_lcdc", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS), - -- /* hclk_video gates */ -+ /* aclk_video gates */ - GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_disp_pre", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS), - - /* xin24m gates */ -@@ -394,7 +407,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { - /* pclk_peri gates */ - GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS), - GATE(0, "pclk_efuse", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS), -- GATE(PCLK_TIMER, "pclk_timer", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), -+ GATE(PCLK_TIMER, "pclk_timer0", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS), - GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS), - GATE(PCLK_SPI, "pclk_spi", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS), - GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS), -@@ -414,6 +427,7 @@ static const char *const rk3036_critical_clocks[] __initconst = { - "aclk_peri", - "hclk_peri", - "pclk_peri", -+ "uart_pll_clk", - }; - - static void __init rk3036_clk_init(struct device_node *np) --- -1.9.1 diff --git a/a/content_digest b/N2/content_digest index 48f0c9c..0adf351 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,16 +1,10 @@ "ref\01929669.AsgMSusdJb@phil\0" "ref\04275248.XCb031JeuI@phil\0" - "From\0Caesar Wang <wxt@rock-chips.com>\0" - "Subject\0Re: [PATCH 3/3] clk: rockchip: include downstream muxes into fractional dividers\0" + "From\0wxt@rock-chips.com (Caesar Wang)\0" + "Subject\0[PATCH 3/3] clk: rockchip: include downstream muxes into fractional dividers\0" "Date\0Sat, 12 Dec 2015 11:35:27 +0800\0" - "To\0Heiko Stuebner <heiko@sntech.de>" - " mturquette@baylibre.com\0" - "Cc\0linux-rockchip@lists.infradead.org" - sjoerd.simons@collabora.co.uk - sboyd@codeaurora.org - linux-clk@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "Hi Heiko,\n" "\n" @@ -24,7 +18,7 @@ "Anyway, I will send the patch for RK3036 if this patch has merged into \n" "mainline.\n" "\n" - "\345\234\250 2015\345\271\26408\346\234\21022\346\227\245 01:48, Heiko Stuebner \345\206\231\351\201\223:\n" + "? 2015?08?22? 01:48, Heiko Stuebner ??:\n" "> Use the newly introduced possibility to combine the fractional dividers\n" "> with their downstream muxes for all fractional dividers on currently\n" "> supported Rockchip SoCs.\n" @@ -299,222 +293,14 @@ "\n" "\n" "-- \n" - caesar wang | software engineer | wxt@rock-chip.com - "\01:2\0" - "fn\00001-clk-rockchip-include-downstream-muxes-into-fractiona.patch\0" - "b\0" - ">From 390af4a7e1d35fd44b73124a397da90b6cdeb021 Mon Sep 17 00:00:00 2001\n" - "From: Caesar Wang <wxt@rock-chips.com>\n" - "Date: Sat, 12 Dec 2015 11:24:20 +0800\n" - "Subject: [PATCH] clk: rockchip: include downstream muxes into fractional\n" - " dividers\n" - "\n" - "Use the newly introduced possibility to combine the fractional dividers\n" - "with their downstream muxes for all fractional dividers on currently\n" - "supported RK3036 SoCs.\n" + "caesar wang | software engineer | wxt at rock-chip.com\n" "\n" - "Change-Id: I03ad115ddb007dc7d15acd5647d2bd1a81d6f884\n" - "Signed-off-by: Caesar Wang <wxt@rock-chips.com>\n" - "---\n" - " drivers/clk/rockchip/clk-rk3036.c | 60 ++++++++++++++++++++++++---------------\n" - " 1 file changed, 37 insertions(+), 23 deletions(-)\n" - "\n" - "diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c\n" - "index 77a9d75..5fb7171 100644\n" - "--- a/drivers/clk/rockchip/clk-rk3036.c\n" - "+++ b/drivers/clk/rockchip/clk-rk3036.c\n" - "@@ -154,6 +154,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t * Clock-Architecture Diagram 1\n" - " \t */\n" - " \n" - "+\t/* PD_CORE */\n" - " \tGATE(0, \"gpll_armclk\", \"gpll\", CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 6, GFLAGS),\n" - " \n" - "@@ -161,6 +162,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t * Clock-Architecture Diagram 2\n" - " \t */\n" - " \n" - "+\t/* PD_DDR */\n" - " \tGATE(0, \"dpll_ddr\", \"dpll\", CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 2, GFLAGS),\n" - " \tGATE(0, \"gpll_ddr\", \"gpll\", CLK_IGNORE_UNUSED,\n" - "@@ -168,6 +170,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \tCOMPOSITE_NOGATE(0, \"ddrphy2x\", mux_ddrphy_p, CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),\n" - " \n" - "+\t/* PD_CORE */\n" - " \tCOMPOSITE_NOMUX(0, \"pclk_dbg\", \"armclk\", CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 7, GFLAGS),\n" - "@@ -175,6 +178,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t\t\tRK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 7, GFLAGS),\n" - " \n" - "+\t/* PD_CPU (BUS) */\n" - " \tGATE(0, \"dpll_cpu\", \"dpll\", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),\n" - " \tGATE(0, \"gpll_cpu\", \"gpll\", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),\n" - " \tCOMPOSITE_NOGATE(0, \"aclk_cpu_src\", mux_busclk_p, 0,\n" - "@@ -188,21 +192,25 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t\t\tRK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 4, GFLAGS),\n" - " \n" - "+\t/* PD_PERI */\n" - " \tCOMPOSITE(0, \"aclk_peri_src\", mux_pll_src_3plls_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 0, GFLAGS),\n" - " \n" - " \tGATE(ACLK_PERI, \"aclk_peri\", \"aclk_peri_src\", 0,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 1, GFLAGS),\n" - "+\t/* pclk_peri_src is soure for timers */\n" - " \tDIV(0, \"pclk_peri_src\", \"aclk_peri_src\", CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),\n" - " \tGATE(PCLK_PERI, \"pclk_peri\", \"pclk_peri_src\", 0,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 3, GFLAGS),\n" - "+\t/* hclk_peri_src is soure for sclk_macref_out */\n" - " \tDIV(0, \"hclk_peri_src\", \"aclk_peri_src\", CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),\n" - " \tGATE(HCLK_PERI, \"hclk_peri\", \"hclk_peri_src\", 0,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 2, GFLAGS),\n" - " \n" - "+\t/* PD_TIMER */\n" - " \tCOMPOSITE_NODIV(SCLK_TIMER0, \"sclk_timer0\", mux_timer_p, CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKSEL_CON(2), 4, 1, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(1), 0, GFLAGS),\n" - "@@ -216,6 +224,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t\t\tRK2928_CLKSEL_CON(2), 7, 1, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 5, GFLAGS),\n" - " \n" - "+\t/* PD_UART */\n" - " \tMUX(0, \"uart_pll_clk\", mux_pll_src_apll_dpll_gpll_usb480m_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(13), 10, 2, MFLAGS),\n" - " \tCOMPOSITE_NOMUX(0, \"uart0_src\", \"uart_pll_clk\", 0,\n" - "@@ -227,22 +236,23 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \tCOMPOSITE_NOMUX(0, \"uart2_src\", \"uart_pll_clk\", 0,\n" - " \t\t\tRK2928_CLKSEL_CON(13), 0, 7, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(1), 8, GFLAGS),\n" - "-\tCOMPOSITE_FRAC(0, \"uart0_frac\", \"uart0_src\", CLK_SET_RATE_PARENT,\n" - "+\tCOMPOSITE_FRACMUX(0, \"uart0_frac\", \"uart0_src\", CLK_SET_RATE_PARENT,\n" - " \t\t\tRK2928_CLKSEL_CON(17), 0,\n" - "-\t\t\tRK2928_CLKGATE_CON(1), 9, GFLAGS),\n" - "-\tCOMPOSITE_FRAC(0, \"uart1_frac\", \"uart1_src\", CLK_SET_RATE_PARENT,\n" - "+\t\t\tRK2928_CLKGATE_CON(1), 9, GFLAGS,\n" - "+\t\tMUX(SCLK_UART0, \"sclk_uart0\", mux_uart0_p, CLK_SET_RATE_PARENT,\n" - "+\t\t\t\tRK2928_CLKSEL_CON(13), 8, 2, MFLAGS)),\n" - "+\tCOMPOSITE_FRACMUX(0, \"uart1_frac\", \"uart1_src\", CLK_SET_RATE_PARENT,\n" - " \t\t\tRK2928_CLKSEL_CON(18), 0,\n" - "-\t\t\tRK2928_CLKGATE_CON(1), 11, GFLAGS),\n" - "-\tCOMPOSITE_FRAC(0, \"uart2_frac\", \"uart2_src\", CLK_SET_RATE_PARENT,\n" - "+\t\t\tRK2928_CLKGATE_CON(1), 11, GFLAGS,\n" - "+\t\tMUX(SCLK_UART1, \"sclk_uart1\", mux_uart1_p, CLK_SET_RATE_PARENT,\n" - "+\t\t\t\tRK2928_CLKSEL_CON(14), 8, 2, MFLAGS)),\n" - "+\tCOMPOSITE_FRACMUX(0, \"uart2_frac\", \"uart2_src\", CLK_SET_RATE_PARENT,\n" - " \t\t\tRK2928_CLKSEL_CON(19), 0,\n" - "-\t\t\tRK2928_CLKGATE_CON(1), 13, GFLAGS),\n" - "-\tMUX(SCLK_UART0, \"sclk_uart0\", mux_uart0_p, CLK_SET_RATE_PARENT,\n" - "-\t\t\tRK2928_CLKSEL_CON(13), 8, 2, MFLAGS),\n" - "-\tMUX(SCLK_UART1, \"sclk_uart1\", mux_uart1_p, CLK_SET_RATE_PARENT,\n" - "-\t\t\tRK2928_CLKSEL_CON(14), 8, 2, MFLAGS),\n" - "-\tMUX(SCLK_UART2, \"sclk_uart2\", mux_uart2_p, CLK_SET_RATE_PARENT,\n" - "-\t\t\tRK2928_CLKSEL_CON(15), 8, 2, MFLAGS),\n" - "+\t\t\tRK2928_CLKGATE_CON(1), 13, GFLAGS,\n" - "+\t\tMUX(SCLK_UART2, \"sclk_uart2\", mux_uart2_p, CLK_SET_RATE_PARENT,\n" - "+\t\t\t\tRK2928_CLKSEL_CON(15), 8, 2, MFLAGS)),\n" - " \n" - "+\t/* PD_VIDEO */\n" - " \tCOMPOSITE(0, \"aclk_vcodec\", mux_pll_src_3plls_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(3), 11, GFLAGS),\n" - "@@ -251,6 +261,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t\t\tRK2928_CLKSEL_CON(20), 0, 2, MFLAGS, 2, 5, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(10), 6, GFLAGS),\n" - " \n" - "+\t/* PD_VIO */\n" - " \tCOMPOSITE(0, \"aclk_disp1_pre\", mux_pll_src_3plls_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(1), 4, GFLAGS),\n" - "@@ -261,6 +272,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t\t\tRK2928_CLKSEL_CON(28), 0, 2, MFLAGS, 8, 8, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(3), 2, GFLAGS),\n" - " \n" - "+\t/* MMC */\n" - " \tCOMPOSITE_NODIV(0, \"sclk_sdmmc_src\", mux_mmc_src_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(12), 8, 2, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 11, GFLAGS),\n" - "@@ -286,28 +298,30 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \tMMC(SCLK_EMMC_DRV, \"emmc_drv\", \"sclk_emmc\", RK3036_EMMC_CON0, 1),\n" - " \tMMC(SCLK_EMMC_SAMPLE, \"emmc_sample\", \"sclk_emmc\", RK3036_EMMC_CON1, 0),\n" - " \n" - "+\t/* I2S */\n" - " \tCOMPOSITE(0, \"i2s_src\", mux_pll_src_3plls_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(3), 14, 2, MFLAGS, 0, 7, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 9, GFLAGS),\n" - "-\tCOMPOSITE_FRAC(0, \"i2s_frac\", \"i2s_src\", CLK_SET_RATE_PARENT,\n" - "+\tCOMPOSITE_FRACMUX(0, \"i2s_frac\", \"i2s_src\", CLK_SET_RATE_PARENT,\n" - " \t\t\tRK2928_CLKSEL_CON(7), 0,\n" - "-\t\t\tRK2928_CLKGATE_CON(0), 10, GFLAGS),\n" - "-\tMUX(0, \"i2s_pre\", mux_i2s_pre_p, CLK_SET_RATE_PARENT,\n" - "-\t\t\tRK2928_CLKSEL_CON(3), 8, 2, MFLAGS),\n" - "+\t\t\tRK2928_CLKGATE_CON(0), 10, GFLAGS,\n" - "+\t\tMUX(0, \"i2s_pre\", mux_i2s_pre_p, CLK_SET_RATE_PARENT,\n" - "+\t\t\t\tRK2928_CLKSEL_CON(3), 8, 2, MFLAGS)),\n" - " \tCOMPOSITE_NODIV(SCLK_I2S_OUT, \"i2s_clkout\", mux_i2s_clkout_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(3), 12, 1, MFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 13, GFLAGS),\n" - " \tGATE(SCLK_I2S, \"sclk_i2s\", \"i2s_pre\", CLK_SET_RATE_PARENT,\n" - " \t\t\tRK2928_CLKGATE_CON(0), 14, GFLAGS),\n" - " \n" - "+\t/* SPDIF */\n" - " \tCOMPOSITE(0, \"spdif_src\", mux_pll_src_3plls_p, 0,\n" - " \t\t\tRK2928_CLKSEL_CON(5), 10, 2, MFLAGS, 0, 7, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 10, GFLAGS),\n" - "-\tCOMPOSITE_FRAC(0, \"spdif_frac\", \"spdif_src\", 0,\n" - "+\tCOMPOSITE_FRACMUX(0, \"spdif_frac\", \"spdif_src\", 0,\n" - " \t\t\tRK2928_CLKSEL_CON(9), 0,\n" - "-\t\t\tRK2928_CLKGATE_CON(2), 12, GFLAGS),\n" - "-\tMUX(SCLK_SPDIF, \"sclk_spdif\", mux_spdif_p, 0,\n" - "-\t\t\tRK2928_CLKSEL_CON(5), 8, 2, MFLAGS),\n" - "+\t\t\tRK2928_CLKGATE_CON(2), 12, GFLAGS,\n" - "+\t\tMUX(SCLK_SPDIF, \"sclk_spdif\", mux_spdif_p, 0,\n" - "+\t\t\t\tRK2928_CLKSEL_CON(5), 8, 2, MFLAGS)),\n" - " \n" - " \tGATE(SCLK_OTGPHY0, \"sclk_otgphy0\", \"xin12m\", CLK_IGNORE_UNUSED,\n" - " \t\t\tRK2928_CLKGATE_CON(1), 5, GFLAGS),\n" - "@@ -332,7 +346,6 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t\t\tRK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),\n" - " \tMUX(SCLK_MACREF, \"mac_clk_ref\", mux_mac_p, CLK_SET_RATE_PARENT,\n" - " \t\t\tRK2928_CLKSEL_CON(21), 3, 1, MFLAGS),\n" - "-\n" - " \tCOMPOSITE_NOMUX(SCLK_MAC, \"mac_clk\", \"mac_clk_ref\", 0,\n" - " \t\t\tRK2928_CLKSEL_CON(21), 9, 5, DFLAGS,\n" - " \t\t\tRK2928_CLKGATE_CON(2), 6, GFLAGS),\n" - "@@ -364,7 +377,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \tGATE(HCLK_VIO_BUS, \"hclk_vio_bus\", \"hclk_disp_pre\", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),\n" - " \tGATE(HCLK_LCDC, \"hclk_lcdc\", \"hclk_disp_pre\", 0, RK2928_CLKGATE_CON(9), 5, GFLAGS),\n" - " \n" - "-\t/* hclk_video gates */\n" - "+\t/* aclk_video gates */\n" - " \tGATE(HCLK_VCODEC, \"hclk_vcodec\", \"hclk_disp_pre\", 0, RK2928_CLKGATE_CON(3), 12, GFLAGS),\n" - " \n" - " \t/* xin24m gates */\n" - "@@ -394,7 +407,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {\n" - " \t/* pclk_peri gates */\n" - " \tGATE(0, \"pclk_peri_matrix\", \"pclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 1, GFLAGS),\n" - " \tGATE(0, \"pclk_efuse\", \"pclk_peri\", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 2, GFLAGS),\n" - "-\tGATE(PCLK_TIMER, \"pclk_timer\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),\n" - "+\tGATE(PCLK_TIMER, \"pclk_timer0\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(7), 7, GFLAGS),\n" - " \tGATE(PCLK_PWM, \"pclk_pwm\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),\n" - " \tGATE(PCLK_SPI, \"pclk_spi\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(7), 12, GFLAGS),\n" - " \tGATE(PCLK_WDT, \"pclk_wdt\", \"pclk_peri\", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),\n" - "@@ -414,6 +427,7 @@ static const char *const rk3036_critical_clocks[] __initconst = {\n" - " \t\"aclk_peri\",\n" - " \t\"hclk_peri\",\n" - " \t\"pclk_peri\",\n" - "+\t\"uart_pll_clk\",\n" - " };\n" - " \n" - " static void __init rk3036_clk_init(struct device_node *np)\n" - "-- \n" - 1.9.1 + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: 0001-clk-rockchip-include-downstream-muxes-into-fractiona.patch\n" + "Type: text/x-patch\n" + "Size: 9718 bytes\n" + "Desc: not available\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151212/fb67e321/attachment.bin> -c2f0f2544a02d4f2b01229eba5e9fcfc4830767f0356c1833010e64faec1d683 +5147e60e9284327ce87cb89e748ba88a3c899e11b48a1495719fd80c4e601610
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