From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH] x86/VPMU: Check more carefully which bits are allowed to be written to MSRs Date: Wed, 23 Dec 2015 10:03:56 -0500 Message-ID: <567AB7DC.80708@oracle.com> References: <1450801483-3698-1-git-send-email-boris.ostrovsky@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: "Tian, Kevin" , "Nakajima, Jun" , "keir@xen.org" , "jbeulich@suse.com" , "andrew.cooper3@citrix.com" Cc: "dietmar.hahn@ts.fujitsu.com" , "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org On 12/23/2015 12:21 AM, Tian, Kevin wrote: >> From: Boris Ostrovsky [mailto:boris.ostrovsky@oracle.com] >> Sent: Wednesday, December 23, 2015 12:25 AM >> >> Current Intel VPMU emulation needs to perform more checks when writing >> PMU MSRs on guest's behalf: >> * MSR_CORE_PERF_GLOBAL_CTRL is not checked at all >> * MSR_CORE_PERF_FIXED_CTR_CTRL has more reserved bits in PMU version 2 >> * MSR_CORE_PERF_GLOBAL_OVF_CTRL's bit 61 is allowed on versions greater >> * than 2. >> >> We can also use precomputed mask in core2_vpmu_do_interrupt(). >> >> Signed-off-by: Boris Ostrovsky > Acked-by: Kevin Tian I think I missed one more register. Let me send another version. -boris