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Mon, 14 Sep 2026 01:20:14 -0700 (PDT) Message-ID: <567c2221-7237-41c9-84a2-6e6865b27617@gmail.com> Date: Mon, 14 Sep 2026 10:20:11 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Janani Sunil Subject: Re: [PATCH v7 07/17] iio: adc: ad7768: Add power mode helper To: Jonathan Cameron , Janani Sunil Cc: =?UTF-8?Q?Nuno_S=C3=A1?= , Michael Hennerich , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Jonathan Corbet , Shuah Khan , Michael Walle , Randy Dunlap , linux@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org, =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= References: <20260910-ad7768-driver-v7-0-7f70b07627e1@analog.com> <20260910-ad7768-driver-v7-7-7f70b07627e1@analog.com> <178933271416.413489.11205164036404426330.b4-review@b4> Content-Language: en-US In-Reply-To: <178933271416.413489.11205164036404426330.b4-review@b4> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/13/26 22:51, Jonathan Cameron wrote: >> +static int ad7768_set_power_mode(struct ad7768_state *st, >> + unsigned int mode_idx) >> +{ >> + const struct ad7768_power_mode_info *mode_info; >> + int ret; >> + >> + mode_info = &ad7768_power_modes[mode_idx]; >> + ret = regmap_update_bits(st->regmap, AD7768_REG_POWER_MODE, >> + AD7768_POWER_MODE_POWER_MODE_MSK | >> + AD7768_POWER_MODE_MCLK_DIV_MSK, >> + FIELD_PREP(AD7768_POWER_MODE_POWER_MODE_MSK, >> + mode_info->mode) | >> + FIELD_PREP(AD7768_POWER_MODE_MCLK_DIV_MSK, >> + mode_info->mode)); > Sashiko: > [Severity: High] > When configuring MEDIAN mode via ad7768_set_power_mode(), does this code > inadvertently configure the MCLK_DIV bitfield using the power mode > register value instead of the correct clock divider register code? > > For MEDIAN power mode, mode_info->mode is 0x2. Writing 0x2 to the MCLK_DIV > bitfield sets the hardware divider to 4 (MCLK/4), instead of the expected > divider of 8 (MCLK/8, which requires register value 0x1). > > Since ad7768_power_modes correctly defines mclk_div = 8 for MEDIAN mode, the > software will calculate output rates and delays based on a divider of 8, while > the hardware runs twice as fast. > - > I haven't looked into this one so please check it out. Both Median power mode and its corresponding MCLK divider use 0b10 register encoding. So using mode_info->mode for both the fields is intentional and logically right. Best Regards, Jan