From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark yao Subject: Re: [PATCH v2 2/3] drm/rockchip: vop: add rk3229 vop support Date: Wed, 06 Jan 2016 08:56:48 +0800 Message-ID: <568C6650.5040708@rock-chips.com> References: <1451965688-12286-1-git-send-email-ykk@rock-chips.com> <1451966307-12642-1-git-send-email-ykk@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1451966307-12642-1-git-send-email-ykk@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Yakir Yang , Heiko Stuebner , David Airlie Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org T24gMjAxNuW5tDAx5pyIMDXml6UgMTE6NTgsIFlha2lyIFlhbmcgd3JvdGU6Cj4gUkszMjI5IHJl Z2lzdGVycyBsYXlvdXQgaXMgc2ltYWxhciB0byBSSzMyODggbGF5b3V0LCBvbmx5IHRoZQo+IGlu dGVycnVwdXQgcmVnaXN0ZXJzIGlzIGRpZmZlcmVudCB0byBSSzMyODguCj4KPiBSSzMyMjkgc3Vw cG9ydCB0d28gb3ZlcmxheSBwbGFuZSBhbmQgb25lIGh3YyBwbGFuZSwgbWF4IG91dHB1dAo+IHJl c29sdXRpb24gaXMgNEsuIGl0IHN1cHBvcnQgSU9NTVUsIGFuZCBpdHMgSU9NTVUgc2FtZSBhcyBy azMyODgncy4KPgo+IFNpZ25lZC1vZmYtYnk6IFlha2lyIFlhbmcgPHlra0Byb2NrLWNoaXBzLmNv bT4KPiAtLS0KPiBDaGFuZ2VzIGluIHYyOgo+IC0gU2VwYXJhdGUgdGhlIHdyaXRlLW1hc2sgY2hh bmdlcyBvdXQsIGFuZCByZW1vdmUgdGhlIERVTU1ZX0lOVFIgbWFyY29zIChIZWlrbykKPgo+ICAg ZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuYyB8IDExMCArKysrKysr KysrKysrKysrKysrKysrKysrKysrCj4gICBkcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2No aXBfdm9wX3JlZy5oIHwgIDkwICsrKysrKysrKysrKysrKysrKysrKysrCj4gICAyIGZpbGVzIGNo YW5nZWQsIDIwMCBpbnNlcnRpb25zKCspCj4KPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJt L3JvY2tjaGlwL3JvY2tjaGlwX3ZvcF9yZWcuYyBiL2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9y b2NrY2hpcF92b3BfcmVnLmMKPiBpbmRleCA3ZmJhZjc2Li5mMTM1OGY5IDEwMDY0NAo+IC0tLSBh L2RyaXZlcnMvZ3B1L2RybS9yb2NrY2hpcC9yb2NrY2hpcF92b3BfcmVnLmMKPiArKysgYi9kcml2 ZXJzL2dwdS9kcm0vcm9ja2NoaXAvcm9ja2NoaXBfdm9wX3JlZy5jCj4gQEAgLTE5MSw2ICsxOTEs MTE0IEBAIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9wX2RhdGEgcmszMjg4X3ZvcCA9IHsKPiAgIAku d2luX3NpemUgPSBBUlJBWV9TSVpFKHJrMzI4OF92b3Bfd2luX2RhdGEpLAo+ICAgfTsKPiAgIAo+ ICtzdGF0aWMgY29uc3Qgc3RydWN0IHZvcF9zY2xfZXh0ZW5zaW9uIHJrMzIyOV93aW5fZnVsbF9z Y2xfZXh0ID0gewo+ICsJLmNiY3JfdnNkX21vZGUgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NUUkwx LCAweDEsIDMxKSwKPiArCS5jYmNyX3ZzdV9tb2RlID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9DVFJM MSwgMHgxLCAzMCksCj4gKwkuY2Jjcl9oc2RfbW9kZSA9IFZPUF9SRUcoUkszMjI5X1dJTjBfQ1RS TDEsIDB4MywgMjgpLAo+ICsJLmNiY3JfdmVyX3NjbF9tb2RlID0gVk9QX1JFRyhSSzMyMjlfV0lO MF9DVFJMMSwgMHgzLCAyNiksCj4gKwkuY2Jjcl9ob3Jfc2NsX21vZGUgPSBWT1BfUkVHKFJLMzIy OV9XSU4wX0NUUkwxLCAweDMsIDI0KSwKPiArCS55cmdiX3ZzZF9tb2RlID0gVk9QX1JFRyhSSzMy MjlfV0lOMF9DVFJMMSwgMHgxLCAyMyksCj4gKwkueXJnYl92c3VfbW9kZSA9IFZPUF9SRUcoUksz MjI5X1dJTjBfQ1RSTDEsIDB4MSwgMjIpLAo+ICsJLnlyZ2JfaHNkX21vZGUgPSBWT1BfUkVHKFJL MzIyOV9XSU4wX0NUUkwxLCAweDMsIDIwKSwKPiArCS55cmdiX3Zlcl9zY2xfbW9kZSA9IFZPUF9S RUcoUkszMjI5X1dJTjBfQ1RSTDEsIDB4MywgMTgpLAo+ICsJLnlyZ2JfaG9yX3NjbF9tb2RlID0g Vk9QX1JFRyhSSzMyMjlfV0lOMF9DVFJMMSwgMHgzLCAxNiksCj4gKwkubGluZV9sb2FkX21vZGUg PSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NUUkwxLCAweDEsIDE1KSwKPiArCS5jYmNyX2F4aV9nYXRo ZXJfbnVtID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9DVFJMMSwgMHg3LCAxMiksCj4gKwkueXJnYl9h eGlfZ2F0aGVyX251bSA9IFZPUF9SRUcoUkszMjI5X1dJTjBfQ1RSTDEsIDB4ZiwgOCksCj4gKwku dnNkX2NiY3JfZ3QyID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9DVFJMMSwgMHgxLCA3KSwKPiArCS52 c2RfY2Jjcl9ndDQgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NUUkwxLCAweDEsIDYpLAo+ICsJLnZz ZF95cmdiX2d0MiA9IFZPUF9SRUcoUkszMjI5X1dJTjBfQ1RSTDEsIDB4MSwgNSksCj4gKwkudnNk X3lyZ2JfZ3Q0ID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9DVFJMMSwgMHgxLCA0KSwKPiArCS5iaWNf Y29lX3NlbCA9IFZPUF9SRUcoUkszMjI5X1dJTjBfQ1RSTDEsIDB4MywgMiksCj4gKwkuY2Jjcl9h eGlfZ2F0aGVyX2VuID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9DVFJMMSwgMHgxLCAxKSwKPiArCS55 cmdiX2F4aV9nYXRoZXJfZW4gPSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NUUkwxLCAweDEsIDApLAo+ ICsJLmxiX21vZGUgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NUUkwwLCAweDcsIDUpLAo+ICt9Owo+ ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCB2b3Bfc2NsX3JlZ3MgcmszMjI5X3dpbl9mdWxsX3Nj bCA9IHsKPiArCS5leHQgPSAmcmszMjI5X3dpbl9mdWxsX3NjbF9leHQsCj4gKwkuc2NhbGVfeXJn Yl94ID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9TQ0xfRkFDVE9SX1lSR0IsIDB4ZmZmZiwgMHgwKSwK PiArCS5zY2FsZV95cmdiX3kgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX1NDTF9GQUNUT1JfWVJHQiwg MHhmZmZmLCAxNiksCj4gKwkuc2NhbGVfY2Jjcl94ID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9TQ0xf RkFDVE9SX0NCUiwgMHhmZmZmLCAweDApLAo+ICsJLnNjYWxlX2NiY3JfeSA9IFZPUF9SRUcoUksz MjI5X1dJTjBfU0NMX0ZBQ1RPUl9DQlIsIDB4ZmZmZiwgMTYpLAo+ICt9Owo+ICsKPiArc3RhdGlj IGNvbnN0IHN0cnVjdCB2b3Bfd2luX3BoeSByazMyMjlfd2luMDFfZGF0YSA9IHsKPiArCS5zY2wg PSAmcmszMjI5X3dpbl9mdWxsX3NjbCwKPiArCS5kYXRhX2Zvcm1hdHMgPSBmb3JtYXRzX3dpbl9m dWxsLAo+ICsJLm5mb3JtYXRzID0gQVJSQVlfU0laRShmb3JtYXRzX3dpbl9mdWxsKSwKPiArCS5l bmFibGUgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NUUkwwLCAweDEsIDApLAo+ICsJLmZvcm1hdCA9 IFZPUF9SRUcoUkszMjI5X1dJTjBfQ1RSTDAsIDB4NywgMSksCj4gKwkucmJfc3dhcCA9IFZPUF9S RUcoUkszMjI5X1dJTjBfQ1RSTDAsIDB4MSwgMTIpLAo+ICsJLmFjdF9pbmZvID0gVk9QX1JFRyhS SzMyMjlfV0lOMF9BQ1RfSU5GTywgMHgxZmZmMWZmZiwgMCksCj4gKwkuZHNwX2luZm8gPSBWT1Bf UkVHKFJLMzIyOV9XSU4wX0RTUF9JTkZPLCAweDBmZmYwZmZmLCAwKSwKPiArCS5kc3Bfc3QgPSBW T1BfUkVHKFJLMzIyOV9XSU4wX0RTUF9TVCwgMHgxZmZmMWZmZiwgMCksCj4gKwkueXJnYl9tc3Qg PSBWT1BfUkVHKFJLMzIyOV9XSU4wX1lSR0JfTVNULCAweGZmZmZmZmZmLCAwKSwKPiArCS51dl9t c3QgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX0NCUl9NU1QsIDB4ZmZmZmZmZmYsIDApLAo+ICsJLnly Z2JfdmlyID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9WSVIsIDB4M2ZmZiwgMCksCj4gKwkudXZfdmly ID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9WSVIsIDB4M2ZmZiwgMTYpLAo+ICsJLnNyY19hbHBoYV9j dGwgPSBWT1BfUkVHKFJLMzIyOV9XSU4wX1NSQ19BTFBIQV9DVFJMLCAweGZmLCAwKSwKPiArCS5k c3RfYWxwaGFfY3RsID0gVk9QX1JFRyhSSzMyMjlfV0lOMF9EU1RfQUxQSEFfQ1RSTCwgMHhmZiwg MCksCj4gK307Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHZvcF93aW5fZGF0YSByazMyMjlf dm9wX3dpbl9kYXRhW10gPSB7Cj4gKwl7IC5iYXNlID0gMHgwMCwgLnBoeSA9ICZyazMyMjlfd2lu MDFfZGF0YSwKPiArCSAgLnR5cGUgPSBEUk1fUExBTkVfVFlQRV9QUklNQVJZIH0sCj4gKwl7IC5i YXNlID0gMHg0MCwgLnBoeSA9ICZyazMyMjlfd2luMDFfZGF0YSwKPiArCSAgLnR5cGUgPSBEUk1f UExBTkVfVFlQRV9DVVJTT1IgfSwKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgdm9w X2N0cmwgcmszMjI5X2N0cmxfZGF0YSA9IHsKPiArCS5jZmdfZG9uZSA9IFZPUF9SRUcoUkszMjI5 X1JFR19DRkdfRE9ORSwgMHgxLCAwKSwKPiArCS5zdGFuZGJ5ID0gVk9QX1JFRyhSSzMyMjlfU1lT X0NUUkwsIDB4MSwgMjIpLAo+ICsJLmdhdGVfZW4gPSBWT1BfUkVHKFJLMzIyOV9TWVNfQ1RSTCwg MHgxLCAyMyksCj4gKwkubW11X2VuID0gVk9QX1JFRyhSSzMyMjlfU1lTX0NUUkwsIDB4MSwgMjAp LAo+ICsJLnJnYl9lbiA9IFZPUF9SRUcoUkszMjI5X1NZU19DVFJMLCAweDEsIDEyKSwKPiArCS5o ZG1pX2VuID0gVk9QX1JFRyhSSzMyMjlfU1lTX0NUUkwsIDB4MSwgMTMpLAo+ICsJLmVkcF9lbiA9 IFZPUF9SRUcoUkszMjI5X1NZU19DVFJMLCAweDEsIDE0KSwKPiArCS5taXBpX2VuID0gVk9QX1JF RyhSSzMyMjlfU1lTX0NUUkwsIDB4MSwgMTUpLAo+ICsJLmRhdGFfYmxhbmsgPSBWT1BfUkVHKFJL MzIyOV9EU1BfQ1RSTDAsIDB4MSwgMTkpLAo+ICsJLm91dF9tb2RlID0gVk9QX1JFRyhSSzMyMjlf RFNQX0NUUkwwLCAweGYsIDApLAo+ICsJLnBpbl9wb2wgPSBWT1BfUkVHKFJLMzIyOV9EU1BfQ1RS TDEsIDB4ZiwgMjApLAo+ICsJLmRpdGhlcl91cCA9IFZPUF9SRUcoUkszMjI5X0RTUF9DVFJMMSwg MHgxLCA2KSwKPiArCS5odG90YWxfcHcgPSBWT1BfUkVHKFJLMzIyOV9EU1BfSFRPVEFMX0hTX0VO RCwgMHgxZmZmMWZmZiwgMCksCj4gKwkuaGFjdF9zdF9lbmQgPSBWT1BfUkVHKFJLMzIyOV9EU1Bf SEFDVF9TVF9FTkQsIDB4MWZmZjFmZmYsIDApLAo+ICsJLnZ0b3RhbF9wdyA9IFZPUF9SRUcoUksz MjI5X0RTUF9WVE9UQUxfVlNfRU5ELCAweDFmZmYxZmZmLCAwKSwKPiArCS52YWN0X3N0X2VuZCA9 IFZPUF9SRUcoUkszMjI5X0RTUF9WQUNUX1NUX0VORCwgMHgxZmZmMWZmZiwgMCksCj4gKwkuaHBv c3Rfc3RfZW5kID0gVk9QX1JFRyhSSzMyMjlfUE9TVF9EU1BfSEFDVF9JTkZPLCAweDFmZmYxZmZm LCAwKSwKPiArCS52cG9zdF9zdF9lbmQgPSBWT1BfUkVHKFJLMzIyOV9QT1NUX0RTUF9WQUNUX0lO Rk8sIDB4MWZmZjFmZmYsIDApLAo+ICt9OwoKSGkgWWFraXIKClJLMzIyOSByZWdpc3RlcnMgbGF5 b3V0IGlzIHNpbWFsYXIgdG8gUkszMjg4IGxheW91dCwgaXMgcG9zc2libGUgdG8gcmV1c2Ugcmsz Mjg4IHJlZ2lzdGVyIHRhYmxlPwoKcmszMjI5X2N0cmxfZGF0YSAmIHJrMzIyOV93aW4wMV9kYXRh IHNlZW1zIHNhbWUgYXMgcmszMjg4X2N0cmxfZGF0YSAmIHJrMzI4OF93aW4wMV9kYXRhLgoKVGhh bmtzLgoKLS0gCu+8rWFyayBZYW8KCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVl ZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZv L2RyaS1kZXZlbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752607AbcAFA5D (ORCPT ); Tue, 5 Jan 2016 19:57:03 -0500 Received: from regular1.263xmail.com ([211.150.99.131]:34219 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752506AbcAFA47 (ORCPT ); Tue, 5 Jan 2016 19:56:59 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: mark.yao@rock-chips.com X-FST-TO: linux-rockchip@lists.infradead.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: <88db662576b68ba216c35db062967a87> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <568C6650.5040708@rock-chips.com> Date: Wed, 06 Jan 2016 08:56:48 +0800 From: Mark yao User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Yakir Yang , Heiko Stuebner , David Airlie CC: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v2 2/3] drm/rockchip: vop: add rk3229 vop support References: <1451965688-12286-1-git-send-email-ykk@rock-chips.com> <1451966307-12642-1-git-send-email-ykk@rock-chips.com> In-Reply-To: <1451966307-12642-1-git-send-email-ykk@rock-chips.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016年01月05日 11:58, Yakir Yang wrote: > RK3229 registers layout is simalar to RK3288 layout, only the > interruput registers is different to RK3288. > > RK3229 support two overlay plane and one hwc plane, max output > resolution is 4K. it support IOMMU, and its IOMMU same as rk3288's. > > Signed-off-by: Yakir Yang > --- > Changes in v2: > - Separate the write-mask changes out, and remove the DUMMY_INTR marcos (Heiko) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 110 ++++++++++++++++++++++++++++ > drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 90 +++++++++++++++++++++++ > 2 files changed, 200 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 7fbaf76..f1358f9 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -191,6 +191,114 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > +static const struct vop_scl_extension rk3229_win_full_scl_ext = { > + .cbcr_vsd_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 31), > + .cbcr_vsu_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 30), > + .cbcr_hsd_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 28), > + .cbcr_ver_scl_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 26), > + .cbcr_hor_scl_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 24), > + .yrgb_vsd_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 23), > + .yrgb_vsu_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 22), > + .yrgb_hsd_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 20), > + .yrgb_ver_scl_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 18), > + .yrgb_hor_scl_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 16), > + .line_load_mode = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 15), > + .cbcr_axi_gather_num = VOP_REG(RK3229_WIN0_CTRL1, 0x7, 12), > + .yrgb_axi_gather_num = VOP_REG(RK3229_WIN0_CTRL1, 0xf, 8), > + .vsd_cbcr_gt2 = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 7), > + .vsd_cbcr_gt4 = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 6), > + .vsd_yrgb_gt2 = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 5), > + .vsd_yrgb_gt4 = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 4), > + .bic_coe_sel = VOP_REG(RK3229_WIN0_CTRL1, 0x3, 2), > + .cbcr_axi_gather_en = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 1), > + .yrgb_axi_gather_en = VOP_REG(RK3229_WIN0_CTRL1, 0x1, 0), > + .lb_mode = VOP_REG(RK3229_WIN0_CTRL0, 0x7, 5), > +}; > + > +static const struct vop_scl_regs rk3229_win_full_scl = { > + .ext = &rk3229_win_full_scl_ext, > + .scale_yrgb_x = VOP_REG(RK3229_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3229_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3229_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3229_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3229_win01_data = { > + .scl = &rk3229_win_full_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3229_WIN0_CTRL0, 0x1, 0), > + .format = VOP_REG(RK3229_WIN0_CTRL0, 0x7, 1), > + .rb_swap = VOP_REG(RK3229_WIN0_CTRL0, 0x1, 12), > + .act_info = VOP_REG(RK3229_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3229_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3229_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3229_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3229_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3229_WIN0_VIR, 0x3fff, 0), > + .uv_vir = VOP_REG(RK3229_WIN0_VIR, 0x3fff, 16), > + .src_alpha_ctl = VOP_REG(RK3229_WIN0_SRC_ALPHA_CTRL, 0xff, 0), > + .dst_alpha_ctl = VOP_REG(RK3229_WIN0_DST_ALPHA_CTRL, 0xff, 0), > +}; > + > +static const struct vop_win_data rk3229_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3229_win01_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x40, .phy = &rk3229_win01_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const struct vop_ctrl rk3229_ctrl_data = { > + .cfg_done = VOP_REG(RK3229_REG_CFG_DONE, 0x1, 0), > + .standby = VOP_REG(RK3229_SYS_CTRL, 0x1, 22), > + .gate_en = VOP_REG(RK3229_SYS_CTRL, 0x1, 23), > + .mmu_en = VOP_REG(RK3229_SYS_CTRL, 0x1, 20), > + .rgb_en = VOP_REG(RK3229_SYS_CTRL, 0x1, 12), > + .hdmi_en = VOP_REG(RK3229_SYS_CTRL, 0x1, 13), > + .edp_en = VOP_REG(RK3229_SYS_CTRL, 0x1, 14), > + .mipi_en = VOP_REG(RK3229_SYS_CTRL, 0x1, 15), > + .data_blank = VOP_REG(RK3229_DSP_CTRL0, 0x1, 19), > + .out_mode = VOP_REG(RK3229_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3229_DSP_CTRL1, 0xf, 20), > + .dither_up = VOP_REG(RK3229_DSP_CTRL1, 0x1, 6), > + .htotal_pw = VOP_REG(RK3229_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3229_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3229_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3229_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .hpost_st_end = VOP_REG(RK3229_POST_DSP_HACT_INFO, 0x1fff1fff, 0), > + .vpost_st_end = VOP_REG(RK3229_POST_DSP_VACT_INFO, 0x1fff1fff, 0), > +}; Hi Yakir RK3229 registers layout is simalar to RK3288 layout, is possible to reuse rk3288 register table? rk3229_ctrl_data & rk3229_win01_data seems same as rk3288_ctrl_data & rk3288_win01_data. Thanks. -- Ｍark Yao