From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752112AbcAFGOX (ORCPT ); Wed, 6 Jan 2016 01:14:23 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14273 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750845AbcAFGOV (ORCPT ); Wed, 6 Jan 2016 01:14:21 -0500 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 05 Jan 2016 21:57:47 -0800 Message-ID: <568CAE65.9030001@nvidia.com> Date: Wed, 6 Jan 2016 11:34:21 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Mark Brown CC: , , Subject: Re: [PATCH 2/2] regmap: irq: add support to have callback pre/post irq handling References: <1450788927-22116-1-git-send-email-ldewangan@nvidia.com> <1450788927-22116-2-git-send-email-ldewangan@nvidia.com> <20160105174334.GJ6588@sirena.org.uk> In-Reply-To: <20160105174334.GJ6588@sirena.org.uk> X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRUKMAIL102.nvidia.com (10.25.59.20) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Resending as previous response was denied by linux-kernel due to html format. On Tuesday 05 January 2016 11:13 PM, Mark Brown wrote: > * PGP Signed by an unknown key > > On Tue, Dec 22, 2015 at 06:25:27PM +0530, Laxman Dewangan wrote: >> Some of devices like MAXIM MAX77620 required to have the chip >> specific configuration before processing interrupt and after >> interrupt handling is done. > I'd like to see the user for this... > This will be there in my next coming patches for PMIC driver from Maxim Semiconductor MAX77620/MAX20024. Per datasheet: Upon the interrupt hardware line going low (nIRQ=0), the software is switched to the priority decoder which decides in what order all interrupts to the processor are serviced and therefore, will transfer control to the PMIC interrupt service routine appropriately. * The first task for the processor is to mask the PMIC interrupt by setting GLBLM. o This forces nIRQ to go high-impedance in which case it will be pulled high by the external pull-up resistor. o Forcing nRIQ to go high-impedance ensures that any interrupts that occur within the PMIC while the PMIC interrupt service routine is being executed will cause a subsequent falling edge on the processor interrupt line. * The next task is to read the IRQTOP register and maintain a local copy. Note that IRQTOP is cleared when read. // Handle all interrupts which occurred from PMIC. * Once all interrupts have been checked and serviced, the interrupt service routine un-masks the hardware interrupt line by clearing (GLBLM). And typical code will be: int max77620_top_irq_chip_pre_irq(void *data) { struct max77620_chip *chip = data; ret = max77620_reg_update(chip->dev, MAX77620_PWR_SLAVE, MAX77620_REG_INTENLBT, MAX77620_GLBLM_MASK, MAX77620_GLBLM_MASK); :::: } int max77620_top_irq_chip_post_irq(void *data) { struct max77620_chip *chip = data; ret = max77620_reg_update(chip->dev, MAX77620_PWR_SLAVE, MAX77620_REG_INTENLBT, MAX77620_GLBLM_MASK, 0); :::: } static struct regmap_irq_chip max77620_top_irq_chip = { .pre_irq = max77620_top_irq_chip_pre_irq, .post_irq = max77620_top_irq_chip_post_irq, };