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From: Timur Tabi <timur@tabi.org>
To: "Maciej S. Szmigiero" <mail@maciej.szmigiero.name>,
	"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>,
	Xiubo Li <Xiubo.Lee@gmail.com>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Fabio Estevam <festevam@gmail.com>
Subject: Re: [PATCH 1/3] ASoC: fsl_ssi: mark SACNT register volatile
Date: Sun, 10 Jan 2016 15:33:55 -0600	[thread overview]
Message-ID: <5692CE43.20708@tabi.org> (raw)
In-Reply-To: <56770FE1.4060202@maciej.szmigiero.name>

Maciej S. Szmigiero wrote:
> +	regmap_write(regs, CCSR_SSI_SACNT,
> +			ssi_private->regcache_sacnt);

So I'm not familiar with all of the regcache features, but I understand 
this patch.  I was wondering if it makes sense to write the same exact 
value that was read previously.  Isn't it possible for the WR or RD bits 
to change between fsl_ssi_suspend() and fsl_ssi_resume()?  That is, 
should we be doing this instead?

u32 temp;
regmap_read(regs, CCSR_SSI_SACNT, &temp);
temp &= 0x18; // preserve WR and RD
regmap_write(regs, CCSR_SSI_SACNT, (ssi_private->regcache_sacnt & ~0x18) 
| temp);

  parent reply	other threads:[~2016-01-10 21:33 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-20 20:30 [PATCH 1/3] ASoC: fsl_ssi: mark SACNT register volatile Maciej S. Szmigiero
2015-12-20 20:30 ` Maciej S. Szmigiero
2015-12-23 13:12 ` Fabio Estevam
2015-12-24 16:12 ` [alsa-devel] " Timur Tabi
2016-01-05 14:57   ` Fabio Estevam
2016-01-10 12:22 ` Applied "ASoC: fsl_ssi: mark SACNT register volatile" to the asoc tree Mark Brown
2016-01-10 21:33 ` Timur Tabi [this message]
2016-01-11 15:52   ` [PATCH 1/3] ASoC: fsl_ssi: mark SACNT register volatile Maciej S. Szmigiero
2016-01-11 15:52     ` Maciej S. Szmigiero

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