From mboxrd@z Thu Jan 1 00:00:00 1970 From: k.kozlowski@samsung.com (Krzysztof Kozlowski) Date: Tue, 12 Jan 2016 17:28:55 +0900 Subject: [PATCH v2] arm: irq: l2c: do not print error in case of missing l2c from dtb In-Reply-To: <1452583474-11729-1-git-send-email-andi.shyti@samsung.com> References: <1452582683.7773.102.camel@perches.com> <1452583474-11729-1-git-send-email-andi.shyti@samsung.com> Message-ID: <5694B947.7040207@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 12.01.2016 16:24, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and print just an information in > case of -ENODEV. > > This patch converts the following error message: > > L2C: failed to init: -19 > > to the following info: > > L2C: no controller entry found in the dtb > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > > Signed-off-by: Andi Shyti > Reported-by: Krzysztof Kozlowski > --- > > Thanks Joe, > > makes sense! > > Andi > > arch/arm/kernel/irq.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Works (Odroid XU3, Exynos5422) and looks good for me: Tested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933891AbcALI3D (ORCPT ); Tue, 12 Jan 2016 03:29:03 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:35524 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933570AbcALI3B (ORCPT ); Tue, 12 Jan 2016 03:29:01 -0500 X-AuditID: cbfec7f5-f79b16d000005389-3a-5694b94afc26 Subject: Re: [PATCH v2] arm: irq: l2c: do not print error in case of missing l2c from dtb To: Andi Shyti , linux-arm-kernel@lists.infradead.org References: <1452582683.7773.102.camel@perches.com> <1452583474-11729-1-git-send-email-andi.shyti@samsung.com> Cc: linux@arm.linux.org.uk, tony@atomide.com, robh@kernel.org, tglx@linutronix.de, olof@lixom.net, tomasz.figa@gmail.com, jiang.liu@linux.intel.com, yamada.masahiro@socionext.com, linux-kernel@vger.kernel.org, m.szyprowski@samsung.com, andi@etezian.org From: Krzysztof Kozlowski Message-id: <5694B947.7040207@samsung.com> Date: Tue, 12 Jan 2016 17:28:55 +0900 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-version: 1.0 In-reply-to: <1452583474-11729-1-git-send-email-andi.shyti@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRmVeSWpSXmKPExsVy+t/xK7peO6eEGWx8rmOx/cgzVovFP54z Wczavp/F4vULQ4tNj6+xWlzeNYfN4vZlXou1R+6yW5y6/pnN4v+eHewWmzdNZbZYtesPo8X+ K14We+99ZnTg82hp7mHz+PZ1EovH9SWfmD12zrrL7rFpVSebx7tz59g95p0M9Ni8pN7jyokm Vo++LasYPU5M/87i8XmTXABPFJdNSmpOZllqkb5dAldG+46PzAXXOSr+N79mbmB8x9bFyMkh IWAiMX3De3YIW0ziwr31QHEuDiGBpYwSPe/2QDlPGSVWXGtlBakSFoiW6Gv9B9YhIuArsWDv C5YuRg6gogKJ62e5QcLMAk1MEhMuVILYbALGEpuXLwFbxiugJbH9zSywMSwCqhK/VqxmBWkV FYiQWLQjE6JEUOLH5HssIDangLvErctbmUFKmAX0JO5f1IKYLi+xec1b5gmMArOQdMxCqJqF pGoBI/MqRtHU0uSC4qT0XCO94sTc4tK8dL3k/NxNjJAI+7qDcekxq0OMAhyMSjy8GexTwoRY E8uKK3MPMUpwMCuJ8NptAQrxpiRWVqUW5ccXleakFh9ilOZgURLnnbnrfYiQQHpiSWp2ampB ahFMlomDU6qB0fnu2Re7yw2dG/Lfznqd/CTw6Lao3JlL5X6Kqp6x+DZTtmDy2n+Lfv6auyn/ Y2Krj/mtXLbT3gmfZtj564hZHciw03j0tsZp2QPVqg3fqn6tcWg1n1kdt1+3RW/zgomTb7a7 y+nrdHD5HpnetupPPP8WmXaB2U+tqs7e6SsKzTxUsq5IfeuF10osxRmJhlrMRcWJAMBmI0is AgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12.01.2016 16:24, Andi Shyti wrote: > In some architectures the L2 cache controller is integrated in the > processor's block itself and it doesn't use any external cache > controller. This means that an entry in the board's dtb related > to the l2c is not necessary. > > Distinguish between error codes and print just an information in > case of -ENODEV. > > This patch converts the following error message: > > L2C: failed to init: -19 > > to the following info: > > L2C: no controller entry found in the dtb > > on boards like odroid-xu4, cortex A7/A15, which don't have > external cache controller. > > Signed-off-by: Andi Shyti > Reported-by: Krzysztof Kozlowski > --- > > Thanks Joe, > > makes sense! > > Andi > > arch/arm/kernel/irq.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Works (Odroid XU3, Exynos5422) and looks good for me: Tested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof