From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54289) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJk34-0000SN-Iw for qemu-devel@nongnu.org; Thu, 14 Jan 2016 10:42:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aJk31-0000QW-3I for qemu-devel@nongnu.org; Thu, 14 Jan 2016 10:42:54 -0500 Received: from mout.web.de ([212.227.17.11]:51062) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJk30-0000QJ-QK for qemu-devel@nongnu.org; Thu, 14 Jan 2016 10:42:51 -0500 References: <1452758668-19284-1-git-send-email-davidkiarie4@gmail.com> <1452758668-19284-4-git-send-email-davidkiarie4@gmail.com> <20160114100946.GA13170@redhat.com> <20160114173824-mutt-send-email-mst@redhat.com> From: Jan Kiszka Message-ID: <5697C1F2.109@web.de> Date: Thu, 14 Jan 2016 16:42:42 +0100 MIME-Version: 1.0 In-Reply-To: <20160114173824-mutt-send-email-mst@redhat.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="rWxtJXxXLN0xE4l3omIKJMT0H6n2nlIQi" Subject: Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" , David kiarie Cc: marcel@redhat.com, Valentine Sinitsyn , Peter Crosthwaite , QEMU Developers This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --rWxtJXxXLN0xE4l3omIKJMT0H6n2nlIQi Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable On 2016-01-14 16:39, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote: >> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin w= rote: >>> On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote: >>>> Add IVRS table for AMD IO MMU. Also reverve MMIO >>> >>> reserve? >> >> Yeah, typo. >> >>> >>>> region for IO MMU via ACPI >>> >>> >>> It does not look like you reserve anything. >>> >>> Pls add a link to hardware spec (in >>> the device implementation) so we can check >>> what does real hardware do. >>> >>> If this is it: >>> http://developer.amd.com/wordpress/media/2012/10/488821.pdf >>> >>> then the way that works seems to be by guest >>> programming the MMIO base. >>> We should do the same: patch seabios and EFI to do this. >> >> Yes, that's the spec. >> >> We thought this could be possible via ACPI (without patching BIOS ), n= o ? >=20 > I don't see how. We should do it the way it happens on real hardware. >=20 Doesn't Seabios retrieve certain ACPI fragments from QEMU via a pv-interface by now? Anyway, the question remains where this address comes from: The BIOS, which then writes it into some hw config register and reports it in addition via ACPI or the hardware (hard-wired). Jan --rWxtJXxXLN0xE4l3omIKJMT0H6n2nlIQi Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlaXwfIACgkQitSsb3rl5xS89gCgmT3prBpuZYSnvP7VYD+ZOLsR 0xgAoKMie4U8qKoHQVXZirelG12/z8X6 =OSSH -----END PGP SIGNATURE----- --rWxtJXxXLN0xE4l3omIKJMT0H6n2nlIQi--