From: Marcel Apfelbaum <marcel@redhat.com>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Laszlo Ersek <lersek@redhat.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register
Date: Thu, 14 Jan 2016 19:20:32 +0200 [thread overview]
Message-ID: <5697D8E0.7020909@redhat.com> (raw)
In-Reply-To: <20160114173718-mutt-send-email-mst@redhat.com>
On 01/14/2016 05:37 PM, Michael S. Tsirkin wrote:
> On Thu, Jan 14, 2016 at 05:23:27PM +0200, Marcel Apfelbaum wrote:
>> On 01/14/2016 04:49 PM, Michael S. Tsirkin wrote:
>>> On Thu, Jan 14, 2016 at 03:30:41PM +0100, Laszlo Ersek wrote:
>>>>> 2. The same as with pxb, disable Integrated End points for pxb-pcie.
>>>>
>>>> My vote, without a doubt.
>>>
>>> Yea, me too.
>>>
>>>
>>> On a related note: I wonder whether enough resources will be allocated
>>> to the bridge to actually make it possible to add devices by hotplug
>>> later.
>>>
>>
>> It works the same as with PXB, but now instead of having one internal PCI-bridge,
>> we will have several switches/root ports. Each of them will get the minimum MEM required by
>> PCI bridges,
>
> what does this mean? What if you add a bunch of devices
> with large memory BARs? They won't fit will they?
>
Indeed, devices with over 1 MB (I think) BARs can't be hot-plugged.
This is a known design limitation. We can think of a way to handle this,
but the real reason we have multiple root bridges is to be able to
correlate an assigned device with a NUMA node. In this case the device
will be added more likely at boot time.
I think the first step is to have *some* hot-plug support for pxb/pxb-pcie
with the current constraints, once it works we can think
of a way to make it work for devices with large BARs.
Thanks,
Marcel
>> however the IO will be allocated only if at least one legacy device
>> will be present at boot time. (this is at least what SeaBIOS does, I am going to check OVMF actions)
>>
>> Also related, checking that PCIe native hotplug works for devices behind
>> pxb-pcie bridges is my next step after I fix the current issue.
>>
>> Thanks,
>> Marcel
>>
>>>
>>>>>
>>>>> I am going to look at 1., maybe I is doable in a clean way.
>>>>
>>>> My vote: don't. :)
>>>>
>>>> Thanks
>>>> Laszlo
>>>>
>>>>> Thanks,
>>>>> Marcel
>>>>>
>>>>>
>>>>> [...]
next prev parent reply other threads:[~2016-01-14 17:20 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-11 12:24 [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register Marcel Apfelbaum
2016-01-11 14:07 ` Igor Mammedov
2016-01-11 15:10 ` Marcel Apfelbaum
2016-01-11 16:11 ` Laszlo Ersek
2016-01-11 16:34 ` Marcel Apfelbaum
2016-01-11 17:15 ` Laszlo Ersek
2016-01-11 18:01 ` Marcel Apfelbaum
2016-01-11 18:44 ` Laszlo Ersek
2016-01-11 18:57 ` Marcel Apfelbaum
2016-01-14 12:24 ` Marcel Apfelbaum
2016-01-14 14:30 ` Laszlo Ersek
2016-01-14 14:49 ` Michael S. Tsirkin
2016-01-14 15:23 ` Marcel Apfelbaum
2016-01-14 15:37 ` Michael S. Tsirkin
2016-01-14 17:20 ` Marcel Apfelbaum [this message]
2016-01-14 17:28 ` Michael S. Tsirkin
2016-01-14 18:25 ` Marcel Apfelbaum
2016-01-14 15:14 ` Marcel Apfelbaum
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