All of lore.kernel.org
 help / color / mirror / Atom feed
From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: Programmingkid <programmingkidx@gmail.com>,
	Alexander Graf <agraf@suse.de>,
	david@gibson.dropbear.id.au
Cc: "qemu-ppc@nongnu.org list:PowerPC" <qemu-ppc@nongnu.org>,
	qemu-devel qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] hw/pci-host/uninorth.c: Add support for Apple's PCI bridge register 0x48
Date: Fri, 22 Jan 2016 16:46:08 +0000	[thread overview]
Message-ID: <56A25CD0.4060709@ilande.co.uk> (raw)
In-Reply-To: <96510826-2FD7-4967-9BEC-746DB44A81F8@gmail.com>

On 22/01/16 16:09, Programmingkid wrote:

> Apple has custom PCI bridge registers that are not a part of any known standard. This patch implements register 0x48. With this patch the AppleMacRiscPCI kernel extension no longer prints these error messages for the mac99 target:
> AppleMacRiscPCI: bad range 2(80000000:01000000)
> AppleMacRiscPCI: bad range 2(81000000:00001000)
> AppleMacRiscPCI: bad range 2(81080000:00080000)
> 
> Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
> 
> ---
>  hw/pci-host/uninorth.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c
> index 215b64f..6541b10 100644
> --- a/hw/pci-host/uninorth.c
> +++ b/hw/pci-host/uninorth.c
> @@ -330,6 +330,10 @@ static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
>      d->config[0x0C] = 0x08; // cache_line_size
>      d->config[0x0D] = 0x10; // latency_timer
>      //    d->config[0x34] = 0x80; // capabilities_pointer
> +    d->config[0x48] = 0x0;
> +    d->config[0x49] = 0x0;
> +    d->config[0x4a] = 0x0;
> +    d->config[0x4b] = 0x1;
>  }
>  
>  static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

As this config space register is seemingly an Apple custom option (or at
least I can't find a mention of it in the PCI-PCI bridge spec) I think
this should have a comment explaining exactly what it does, and should
reference both AppleMacRiscPCI.cpp filename and the enum for the
register value (0x48 == kMacRISCPCIAddressSelect).

I'd also like to see a note explaining that this sets up the register to
match the PCI memory region base/size currently used in QEMU/OpenBIOS
too in order to provide a hint that if one changes, so must the other.

BTW is the register required for any of the other uni-north realize
functions? Alex?


ATB,

Mark.

  reply	other threads:[~2016-01-22 16:46 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-22 16:09 [Qemu-devel] [PATCH] hw/pci-host/uninorth.c: Add support for Apple's PCI bridge register 0x48 Programmingkid
2016-01-22 16:46 ` Mark Cave-Ayland [this message]
2016-01-22 18:26   ` Programmingkid
2016-01-22 19:13     ` Mark Cave-Ayland
2016-01-24 23:40       ` David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=56A25CD0.4060709@ilande.co.uk \
    --to=mark.cave-ayland@ilande.co.uk \
    --cc=agraf@suse.de \
    --cc=david@gibson.dropbear.id.au \
    --cc=programmingkidx@gmail.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.