From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leon Alrae Subject: Re: [PATCH v4 7/7] mips/kvm: Support MSA in MIPS KVM guests Date: Tue, 2 Feb 2016 09:58:46 +0000 Message-ID: <56B07DD6.8070203@imgtec.com> References: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> <1450435564-30720-8-git-send-email-james.hogan@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Cc: , Aurelien Jarno To: James Hogan , , Paolo Bonzini Return-path: Received: from mailapp01.imgtec.com ([195.59.15.196]:52063 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754305AbcBBJ6w (ORCPT ); Tue, 2 Feb 2016 04:58:52 -0500 In-Reply-To: <1450435564-30720-8-git-send-email-james.hogan@imgtec.com> Sender: kvm-owner@vger.kernel.org List-ID: Hi James, On 18/12/15 10:46, James Hogan wrote: > @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) > restore_flush_mode(env); > } > > - /* Floating point registers */ > - for (i = 0; i < 32; ++i) { > - if (env->CP0_Status & (1 << CP0St_FR)) { > - err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), > - &env->active_fpu.fpr[i].d); > - } else { > - err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), > - &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); > + /* > + * FPU register state is a subset of MSA vector state, so don't save FPU > + * registers if we're emulating a CPU with MSA. > + */ > + if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { > + /* Floating point registers */ > + for (i = 0; i < 32; ++i) { > + if (env->CP0_Status & (1 << CP0St_FR)) { > + err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), > + &env->active_fpu.fpr[i].d); > + } else { > + err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), > + &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); > + } > + if (err < 0) { > + DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); > + ret = err; > + } > } > + } > + } > + > + /* Only get MSA state if we're emulating a CPU with MSA */ > + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { > + /* MSA Control Registers */ > + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, > + &env->msair); > + if (err < 0) { > + DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); > + ret = err; > + } > + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, > + &env->active_tc.msacsr); > + if (err < 0) { > + DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); > + ret = err; > + } Shouldn't MSA's float_status (i.e. msa_fp_status) be restored to reflect MSACSR? Thanks, Leon > + /* Vector registers (includes FP registers) */ > + for (i = 0; i < 32; ++i) { > + /* Big endian MSA not supported by QEMU yet anyway */ > + err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), > + env->active_fpu.fpr[i].wr.d); > if (err < 0) { > - DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); > + DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); > ret = err; > } > } > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aQXje-0002sD-ON for qemu-devel@nongnu.org; Tue, 02 Feb 2016 04:58:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aQXja-00012r-OY for qemu-devel@nongnu.org; Tue, 02 Feb 2016 04:58:58 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:8542) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aQXja-00012A-I5 for qemu-devel@nongnu.org; Tue, 02 Feb 2016 04:58:54 -0500 References: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com> <1450435564-30720-8-git-send-email-james.hogan@imgtec.com> From: Leon Alrae Message-ID: <56B07DD6.8070203@imgtec.com> Date: Tue, 2 Feb 2016 09:58:46 +0000 MIME-Version: 1.0 In-Reply-To: <1450435564-30720-8-git-send-email-james.hogan@imgtec.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 7/7] mips/kvm: Support MSA in MIPS KVM guests List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: James Hogan , qemu-devel@nongnu.org, Paolo Bonzini Cc: Aurelien Jarno , kvm@vger.kernel.org Hi James, On 18/12/15 10:46, James Hogan wrote: > @@ -611,17 +664,51 @@ static int kvm_mips_get_fpu_registers(CPUState *cs) > restore_flush_mode(env); > } > > - /* Floating point registers */ > - for (i = 0; i < 32; ++i) { > - if (env->CP0_Status & (1 << CP0St_FR)) { > - err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), > - &env->active_fpu.fpr[i].d); > - } else { > - err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), > - &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); > + /* > + * FPU register state is a subset of MSA vector state, so don't save FPU > + * registers if we're emulating a CPU with MSA. > + */ > + if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) { > + /* Floating point registers */ > + for (i = 0; i < 32; ++i) { > + if (env->CP0_Status & (1 << CP0St_FR)) { > + err = kvm_mips_get_one_ureg64(cs, KVM_REG_MIPS_FPR_64(i), > + &env->active_fpu.fpr[i].d); > + } else { > + err = kvm_mips_get_one_ureg(cs, KVM_REG_MIPS_FPR_32(i), > + &env->active_fpu.fpr[i].w[FP_ENDIAN_IDX]); > + } > + if (err < 0) { > + DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); > + ret = err; > + } > } > + } > + } > + > + /* Only get MSA state if we're emulating a CPU with MSA */ > + if (env->CP0_Config3 & (1 << CP0C3_MSAP)) { > + /* MSA Control Registers */ > + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR, > + &env->msair); > + if (err < 0) { > + DPRINTF("%s: Failed to get MSA_IR (%d)\n", __func__, err); > + ret = err; > + } > + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_CSR, > + &env->active_tc.msacsr); > + if (err < 0) { > + DPRINTF("%s: Failed to get MSA_CSR (%d)\n", __func__, err); > + ret = err; > + } Shouldn't MSA's float_status (i.e. msa_fp_status) be restored to reflect MSACSR? Thanks, Leon > + /* Vector registers (includes FP registers) */ > + for (i = 0; i < 32; ++i) { > + /* Big endian MSA not supported by QEMU yet anyway */ > + err = kvm_mips_get_one_reg64(cs, KVM_REG_MIPS_VEC_128(i), > + env->active_fpu.fpr[i].wr.d); > if (err < 0) { > - DPRINTF("%s: Failed to get FPR%u (%d)\n", __func__, i, err); > + DPRINTF("%s: Failed to get VEC%u (%d)\n", __func__, i, err); > ret = err; > } > } >