diff for duplicates of <56B0D83E.5090604@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 7ded434..eb5457d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -11,7 +11,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > reuse the DT for 32-bit kernels as well. > This .dtsi lists the hardware that we support so far. > -> Signed-off-by: Andre Przywara <andre.przywara@arm.com> +> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + @@ -52,7 +52,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: -> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> +> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -114,28 +114,28 @@ On 01/02/16 18:39, Andre Przywara wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; @@ -187,7 +187,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -195,7 +195,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "pll1"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -220,7 +220,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "pll8"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -229,7 +229,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + critical-clocks = <0>; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -237,7 +237,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -245,7 +245,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -253,7 +253,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -261,7 +261,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -269,7 +269,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: clk at 01c20060 { +> + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,a64-bus-gates-clk", > + "allwinner,sunxi-multi-bus-gates-clk"; @@ -336,7 +336,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + }; > + }; > + -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; @@ -354,7 +354,7 @@ Parents are PLL6(2x) and PLL8(2x) according to manual. > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -364,7 +364,7 @@ Parents are PLL6(2x) and PLL8(2x) according to manual. > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -390,7 +390,7 @@ Parents are PLL6(2x) and PLL8(2x) according to manual. > + #size-cells = <1>; > + ranges; > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&bus_gates 8>, @@ -418,7 +418,7 @@ PLL6*2 problem). > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&bus_gates 9>, @@ -437,7 +437,7 @@ PLL6*2 problem). > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&bus_gates 10>, @@ -456,7 +456,7 @@ PLL6*2 problem). > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -468,56 +468,56 @@ PLL6*2 problem). > + interrupt-controller; > + #interrupt-cells = <2>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0 at 1 { +> + uart0_pins_b: uart0@1 { > + allwinner,pins = "PF2", "PF3"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_pins: uart1 at 0 { +> + uart1_pins: uart1@0 { > + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_pins: uart2 at 0 { +> + uart2_pins: uart2@0 { > + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_a: uart3 at 0 { +> + uart3_pins_a: uart3@0 { > + allwinner,pins = "PD0", "PD1"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_b: uart3 at 1 { +> + uart3_pins_b: uart3@1 { > + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart4_pins: uart4 at 0 { +> + uart4_pins: uart4@0 { > + allwinner,pins = "PD2", "PD3", "PD4", "PD5"; > + allwinner,function = "uart4"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_pins: mmc0 at 0 { +> + mmc0_pins: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", "PF3", > + "PF4", "PF5"; > + allwinner,function = "mmc0"; @@ -525,14 +525,14 @@ PLL6*2 problem). > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_default_cd_pin: mmc0_cd_pin at 0 { +> + mmc0_default_cd_pin: mmc0_cd_pin@0 { > + allwinner,pins = "PF6"; > + allwinner,function = "gpio_in"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; > + }; > + -> + mmc1_pins: mmc1 at 0 { +> + mmc1_pins: mmc1@0 { > + allwinner,pins = "PG0", "PG1", "PG2", "PG3", > + "PG4", "PG5"; > + allwinner,function = "mmc1"; @@ -540,7 +540,7 @@ PLL6*2 problem). > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc2_pins: mmc2 at 0 { +> + mmc2_pins: mmc2@0 { > + allwinner,pins = "PC1", "PC5", "PC6", "PC8", > + "PC9", "PC10"; > + allwinner,function = "mmc2"; @@ -549,25 +549,25 @@ PLL6*2 problem). > + }; > + }; > + -> + ahb_rst: reset at 01c202c0 { +> + ahb_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-ahb1-reset"; > + reg = <0x01c202c0 0xc>; > + }; > + -> + apb1_rst: reset at 01c202d0 { +> + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + -> + apb2_rst: reset at 01c202d8 { +> + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -582,7 +582,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart1: serial at 01c28400 { +> + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -594,7 +594,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart2: serial at 01c28800 { +> + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -606,7 +606,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart3: serial at 01c28c00 { +> + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -618,7 +618,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart4: serial at 01c29000 { +> + uart4: serial@01c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -630,7 +630,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + rtc: rtc at 01f00000 { +> + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N1/content_digest index 6221a81..8b02618 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,24 @@ "ref\01454348370-3816-1-git-send-email-andre.przywara@arm.com\0" "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "ref\01454348370-3816-11-git-send-email-andre.przywara-5wv7dgnIgG8@public.gmane.org\0" + "From\0Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Tue, 2 Feb 2016 17:24:30 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0andre.przywara-5wv7dgnIgG8@public.gmane.org" + Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> + Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org\0" + "Cc\0Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>" + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -19,7 +34,7 @@ "> reuse the DT for 32-bit kernels as well.\n" "> This .dtsi lists the hardware that we support so far.\n" "> \n" - "> Signed-off-by: Andre Przywara <andre.przywara@arm.com>\n" + "> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>\n" "> ---\n" "> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +\n" "> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +\n" @@ -60,7 +75,7 @@ "> +/*\n" "> + * Copyright (C) 2016 ARM Ltd.\n" "> + * based on the Allwinner H3 dtsi:\n" - "> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>\n" + "> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -122,28 +137,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -195,7 +210,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -203,7 +218,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -228,7 +243,7 @@ "> +\t\t\tclock-output-names = \"pll8\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -237,7 +252,7 @@ "> +\t\t\tcritical-clocks = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -245,7 +260,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -253,7 +268,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -261,7 +276,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -269,7 +284,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -277,7 +292,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: clk at 01c20060 {\n" + "> +\t\tbus_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" "> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -344,7 +359,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "\n" @@ -362,7 +377,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -372,7 +387,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -398,7 +413,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -426,7 +441,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 9>,\n" @@ -445,7 +460,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 10>,\n" @@ -464,7 +479,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -476,56 +491,56 @@ "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <2>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> +\t\t\tuart0_pins_b: uart0@1 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_pins: uart1 at 0 {\n" + "> +\t\t\tuart1_pins: uart1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_pins: uart2 at 0 {\n" + "> +\t\t\tuart2_pins: uart2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> +\t\t\tuart3_pins_a: uart3@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + "> +\t\t\tuart3_pins_b: uart3@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4_pins: uart4 at 0 {\n" + "> +\t\t\tuart4_pins: uart4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD2\", \"PD3\", \"PD4\", \"PD5\";\n" "> +\t\t\t\tallwinner,function = \"uart4\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_pins: mmc0 at 0 {\n" + "> +\t\t\tmmc0_pins: mmc0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n" "> +\t\t\t\t\t\t \"PF4\", \"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" @@ -533,14 +548,14 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin at 0 {\n" + "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF6\";\n" "> +\t\t\t\tallwinner,function = \"gpio_in\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins: mmc1 at 0 {\n" + "> +\t\t\tmmc1_pins: mmc1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n" "> +\t\t\t\t\t\t \"PG4\", \"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" @@ -548,7 +563,7 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc2_pins: mmc2 at 0 {\n" + "> +\t\t\tmmc2_pins: mmc2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PC1\", \"PC5\", \"PC6\", \"PC8\",\n" "> +\t\t\t\t\t\t \"PC9\", \"PC10\";\n" "> +\t\t\t\tallwinner,function = \"mmc2\";\n" @@ -557,25 +572,25 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb_rst: reset at 01c202c0 {\n" + "> +\t\tahb_rst: reset@01c202c0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-reset\";\n" "> +\t\t\treg = <0x01c202c0 0xc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_rst: reset at 01c202d0 {\n" + "> +\t\tapb1_rst: reset@01c202d0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d0 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_rst: reset at 01c202d8 {\n" + "> +\t\tapb2_rst: reset@01c202d8 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d8 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -590,7 +605,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial at 01c28400 {\n" + "> +\t\tuart1: serial@01c28400 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -602,7 +617,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 01c28800 {\n" + "> +\t\tuart2: serial@01c28800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -614,7 +629,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial at 01c28c00 {\n" + "> +\t\tuart3: serial@01c28c00 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -626,7 +641,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart4: serial at 01c29000 {\n" + "> +\t\tuart4: serial@01c29000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c29000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -638,7 +653,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\trtc: rtc at 01f00000 {\n" + "> +\t\trtc: rtc@01f00000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> +\t\t\treg = <0x01f00000 0x54>;\n" "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -668,4 +683,4 @@ "Regards,\n" Jens -a578e05398b246105d8a71360caf88b9624a806a501f5b6f39f7bf2adb5c9092 +746d1d6a02735e188a7dda9e62e67846608f8026ce68894e37f17cbb86777f77
diff --git a/a/1.txt b/N2/1.txt index 7ded434..f73db18 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -114,28 +114,28 @@ On 01/02/16 18:39, Andre Przywara wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; @@ -187,7 +187,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -195,7 +195,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "pll1"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -220,7 +220,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "pll8"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -229,7 +229,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + critical-clocks = <0>; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -237,7 +237,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -245,7 +245,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -253,7 +253,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -261,7 +261,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -269,7 +269,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: clk at 01c20060 { +> + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,a64-bus-gates-clk", > + "allwinner,sunxi-multi-bus-gates-clk"; @@ -336,7 +336,7 @@ On 01/02/16 18:39, Andre Przywara wrote: > + }; > + }; > + -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; @@ -354,7 +354,7 @@ Parents are PLL6(2x) and PLL8(2x) according to manual. > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -364,7 +364,7 @@ Parents are PLL6(2x) and PLL8(2x) according to manual. > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -390,7 +390,7 @@ Parents are PLL6(2x) and PLL8(2x) according to manual. > + #size-cells = <1>; > + ranges; > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; > + clocks = <&bus_gates 8>, @@ -418,7 +418,7 @@ PLL6*2 problem). > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; > + clocks = <&bus_gates 9>, @@ -437,7 +437,7 @@ PLL6*2 problem). > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; > + clocks = <&bus_gates 10>, @@ -456,7 +456,7 @@ PLL6*2 problem). > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -468,56 +468,56 @@ PLL6*2 problem). > + interrupt-controller; > + #interrupt-cells = <2>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0 at 1 { +> + uart0_pins_b: uart0@1 { > + allwinner,pins = "PF2", "PF3"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_pins: uart1 at 0 { +> + uart1_pins: uart1@0 { > + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_pins: uart2 at 0 { +> + uart2_pins: uart2@0 { > + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_a: uart3 at 0 { +> + uart3_pins_a: uart3@0 { > + allwinner,pins = "PD0", "PD1"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_b: uart3 at 1 { +> + uart3_pins_b: uart3@1 { > + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart4_pins: uart4 at 0 { +> + uart4_pins: uart4@0 { > + allwinner,pins = "PD2", "PD3", "PD4", "PD5"; > + allwinner,function = "uart4"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_pins: mmc0 at 0 { +> + mmc0_pins: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", "PF3", > + "PF4", "PF5"; > + allwinner,function = "mmc0"; @@ -525,14 +525,14 @@ PLL6*2 problem). > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_default_cd_pin: mmc0_cd_pin at 0 { +> + mmc0_default_cd_pin: mmc0_cd_pin@0 { > + allwinner,pins = "PF6"; > + allwinner,function = "gpio_in"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; > + }; > + -> + mmc1_pins: mmc1 at 0 { +> + mmc1_pins: mmc1@0 { > + allwinner,pins = "PG0", "PG1", "PG2", "PG3", > + "PG4", "PG5"; > + allwinner,function = "mmc1"; @@ -540,7 +540,7 @@ PLL6*2 problem). > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc2_pins: mmc2 at 0 { +> + mmc2_pins: mmc2@0 { > + allwinner,pins = "PC1", "PC5", "PC6", "PC8", > + "PC9", "PC10"; > + allwinner,function = "mmc2"; @@ -549,25 +549,25 @@ PLL6*2 problem). > + }; > + }; > + -> + ahb_rst: reset at 01c202c0 { +> + ahb_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-ahb1-reset"; > + reg = <0x01c202c0 0xc>; > + }; > + -> + apb1_rst: reset at 01c202d0 { +> + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + -> + apb2_rst: reset at 01c202d8 { +> + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -582,7 +582,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart1: serial at 01c28400 { +> + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -594,7 +594,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart2: serial at 01c28800 { +> + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -606,7 +606,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart3: serial at 01c28c00 { +> + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -618,7 +618,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + uart4: serial at 01c29000 { +> + uart4: serial@01c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -630,7 +630,7 @@ Do we need reset-names here (and below)? > + status = "disabled"; > + }; > + -> + rtc: rtc at 01f00000 { +> + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, diff --git a/a/content_digest b/N2/content_digest index 6221a81..b418dee 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,23 @@ "ref\01454348370-3816-1-git-send-email-andre.przywara@arm.com\0" "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "From\0Jens Kuske <jenskuske@gmail.com>\0" + "Subject\0Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Tue, 2 Feb 2016 17:24:30 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0andre.przywara@arm.com" + Maxime Ripard <maxime.ripard@free-electrons.com> + Chen-Yu Tsai <wens@csie.org> + " linux-sunxi@googlegroups.com\0" + "Cc\0Arnd Bergmann <arnd@arndb.de>" + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -122,28 +136,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -195,7 +209,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -203,7 +217,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -228,7 +242,7 @@ "> +\t\t\tclock-output-names = \"pll8\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -237,7 +251,7 @@ "> +\t\t\tcritical-clocks = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -245,7 +259,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -253,7 +267,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -261,7 +275,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -269,7 +283,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -277,7 +291,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: clk at 01c20060 {\n" + "> +\t\tbus_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" "> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -344,7 +358,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "\n" @@ -362,7 +376,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -372,7 +386,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -398,7 +412,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -426,7 +440,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 9>,\n" @@ -445,7 +459,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" "> +\t\t\tclocks = <&bus_gates 10>,\n" @@ -464,7 +478,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -476,56 +490,56 @@ "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <2>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> +\t\t\tuart0_pins_b: uart0@1 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_pins: uart1 at 0 {\n" + "> +\t\t\tuart1_pins: uart1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_pins: uart2 at 0 {\n" + "> +\t\t\tuart2_pins: uart2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> +\t\t\tuart3_pins_a: uart3@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + "> +\t\t\tuart3_pins_b: uart3@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4_pins: uart4 at 0 {\n" + "> +\t\t\tuart4_pins: uart4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD2\", \"PD3\", \"PD4\", \"PD5\";\n" "> +\t\t\t\tallwinner,function = \"uart4\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_pins: mmc0 at 0 {\n" + "> +\t\t\tmmc0_pins: mmc0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n" "> +\t\t\t\t\t\t \"PF4\", \"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" @@ -533,14 +547,14 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin at 0 {\n" + "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF6\";\n" "> +\t\t\t\tallwinner,function = \"gpio_in\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins: mmc1 at 0 {\n" + "> +\t\t\tmmc1_pins: mmc1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n" "> +\t\t\t\t\t\t \"PG4\", \"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" @@ -548,7 +562,7 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc2_pins: mmc2 at 0 {\n" + "> +\t\t\tmmc2_pins: mmc2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PC1\", \"PC5\", \"PC6\", \"PC8\",\n" "> +\t\t\t\t\t\t \"PC9\", \"PC10\";\n" "> +\t\t\t\tallwinner,function = \"mmc2\";\n" @@ -557,25 +571,25 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb_rst: reset at 01c202c0 {\n" + "> +\t\tahb_rst: reset@01c202c0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-reset\";\n" "> +\t\t\treg = <0x01c202c0 0xc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_rst: reset at 01c202d0 {\n" + "> +\t\tapb1_rst: reset@01c202d0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d0 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_rst: reset at 01c202d8 {\n" + "> +\t\tapb2_rst: reset@01c202d8 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d8 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -590,7 +604,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial at 01c28400 {\n" + "> +\t\tuart1: serial@01c28400 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -602,7 +616,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 01c28800 {\n" + "> +\t\tuart2: serial@01c28800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -614,7 +628,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial at 01c28c00 {\n" + "> +\t\tuart3: serial@01c28c00 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -626,7 +640,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart4: serial at 01c29000 {\n" + "> +\t\tuart4: serial@01c29000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c29000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -638,7 +652,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\trtc: rtc at 01f00000 {\n" + "> +\t\trtc: rtc@01f00000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> +\t\t\treg = <0x01f00000 0x54>;\n" "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -668,4 +682,4 @@ "Regards,\n" Jens -a578e05398b246105d8a71360caf88b9624a806a501f5b6f39f7bf2adb5c9092 +6e619be8f81616d76ec8572935dfdd5e1171c013696d78bf4adb363247b318ec
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.