diff for duplicates of <56B0EA09.9030107@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 7ad5a0e..fd3988d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -30,7 +30,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html > >>> + ->>> + cpu: cpu_clk at 01c20050 { +>>> + cpu: cpu_clk@01c20050 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-cpu-clk"; >>> + reg = <0x01c20050 0x4>; @@ -39,7 +39,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + critical-clocks = <0>; >>> + }; >>> + ->>> + axi: axi_clk at 01c20050 { +>>> + axi: axi_clk@01c20050 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-axi-clk"; >>> + reg = <0x01c20050 0x4>; @@ -47,7 +47,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "axi"; >>> + }; >>> + ->>> + ahb1: ahb1_clk at 01c20054 { +>>> + ahb1: ahb1_clk@01c20054 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >>> + reg = <0x01c20054 0x4>; @@ -55,7 +55,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "ahb1"; >>> + }; >>> + ->>> + ahb2: ahb2_clk at 01c2005c { +>>> + ahb2: ahb2_clk@01c2005c { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >>> + reg = <0x01c2005c 0x4>; @@ -63,7 +63,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "ahb2"; >>> + }; >>> + ->>> + apb1: apb1_clk at 01c20054 { +>>> + apb1: apb1_clk@01c20054 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-apb0-clk"; >>> + reg = <0x01c20054 0x4>; @@ -71,7 +71,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "apb1"; >>> + }; >>> + ->>> + apb2: apb2_clk at 01c20058 { +>>> + apb2: apb2_clk@01c20058 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-apb1-clk"; >>> + reg = <0x01c20058 0x4>; @@ -79,7 +79,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "apb2"; >>> + }; >>> + ->>> + bus_gates: clk at 01c20060 { +>>> + bus_gates: clk@01c20060 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,a64-bus-gates-clk", >>> + "allwinner,sunxi-multi-bus-gates-clk"; @@ -146,7 +146,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + }; >>> + }; >>> + ->>> + mmc0_clk: clk at 01c20088 { +>>> + mmc0_clk: clk@01c20088 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> @@ -178,7 +178,7 @@ Maximes work. >>> + "mmc0_sample"; >>> + }; >>> + ->>> + mmc1_clk: clk at 01c2008c { +>>> + mmc1_clk: clk@01c2008c { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun4i-a10-mmc-clk"; >>> + reg = <0x01c2008c 0x4>; @@ -188,7 +188,7 @@ Maximes work. >>> + "mmc1_sample"; >>> + }; >>> + ->>> + mmc2_clk: clk at 01c20090 { +>>> + mmc2_clk: clk@01c20090 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun4i-a10-mmc-clk"; >>> + reg = <0x01c20090 0x4>; @@ -214,7 +214,7 @@ Maximes work. >>> + #size-cells = <1>; >>> + ranges; >>> + ->>> + mmc0: mmc at 01c0f000 { +>>> + mmc0: mmc@01c0f000 { >>> + compatible = "allwinner,sun5i-a13-mmc"; >>> + reg = <0x01c0f000 0x1000>; >>> + clocks = <&bus_gates 8>, diff --git a/a/content_digest b/N1/content_digest index 314a930..cee5a36 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,10 +2,25 @@ "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" "ref\056B0D83E.5090604@gmail.com\0" "ref\056B0DD67.3060802@arm.com\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "ref\056B0DD67.3060802-5wv7dgnIgG8@public.gmane.org\0" + "From\0Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Tue, 2 Feb 2016 18:40:25 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0andre.przywara-5wv7dgnIgG8@public.gmane.org\0" + "Cc\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>" + Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org + Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -40,7 +55,7 @@ "\n" ">\n" ">>> +\n" - ">>> +\t\tcpu: cpu_clk at 01c20050 {\n" + ">>> +\t\tcpu: cpu_clk@01c20050 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">>> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -49,7 +64,7 @@ ">>> +\t\t\tcritical-clocks = <0>;\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\taxi: axi_clk at 01c20050 {\n" + ">>> +\t\taxi: axi_clk@01c20050 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">>> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -57,7 +72,7 @@ ">>> +\t\t\tclock-output-names = \"axi\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tahb1: ahb1_clk at 01c20054 {\n" + ">>> +\t\tahb1: ahb1_clk@01c20054 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">>> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -65,7 +80,7 @@ ">>> +\t\t\tclock-output-names = \"ahb1\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tahb2: ahb2_clk at 01c2005c {\n" + ">>> +\t\tahb2: ahb2_clk@01c2005c {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">>> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -73,7 +88,7 @@ ">>> +\t\t\tclock-output-names = \"ahb2\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tapb1: apb1_clk at 01c20054 {\n" + ">>> +\t\tapb1: apb1_clk@01c20054 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">>> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -81,7 +96,7 @@ ">>> +\t\t\tclock-output-names = \"apb1\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tapb2: apb2_clk at 01c20058 {\n" + ">>> +\t\tapb2: apb2_clk@01c20058 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">>> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -89,7 +104,7 @@ ">>> +\t\t\tclock-output-names = \"apb2\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tbus_gates: clk at 01c20060 {\n" + ">>> +\t\tbus_gates: clk@01c20060 {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" ">>> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -156,7 +171,7 @@ ">>> +\t\t\t};\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tmmc0_clk: clk at 01c20088 {\n" + ">>> +\t\tmmc0_clk: clk@01c20088 {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">>\n" @@ -188,7 +203,7 @@ ">>> +\t\t\t\t\t \"mmc0_sample\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tmmc1_clk: clk at 01c2008c {\n" + ">>> +\t\tmmc1_clk: clk@01c2008c {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">>> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -198,7 +213,7 @@ ">>> +\t\t\t\t\t \"mmc1_sample\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tmmc2_clk: clk at 01c20090 {\n" + ">>> +\t\tmmc2_clk: clk@01c20090 {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">>> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -224,7 +239,7 @@ ">>> +\t\t#size-cells = <1>;\n" ">>> +\t\tranges;\n" ">>> +\n" - ">>> +\t\tmmc0: mmc at 01c0f000 {\n" + ">>> +\t\tmmc0: mmc@01c0f000 {\n" ">>> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">>> +\t\t\treg = <0x01c0f000 0x1000>;\n" ">>> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -263,4 +278,4 @@ "\n" Jens -1a11af047a143589ca60ac41ae13e19caa1880524802f8bb995cbc7331ce2055 +087277472374e879e5dc1c07aaf92ef1140e259c05629cd050336358905cb51a
diff --git a/a/1.txt b/N2/1.txt index 7ad5a0e..fd3988d 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -30,7 +30,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html > >>> + ->>> + cpu: cpu_clk at 01c20050 { +>>> + cpu: cpu_clk@01c20050 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-cpu-clk"; >>> + reg = <0x01c20050 0x4>; @@ -39,7 +39,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + critical-clocks = <0>; >>> + }; >>> + ->>> + axi: axi_clk at 01c20050 { +>>> + axi: axi_clk@01c20050 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-axi-clk"; >>> + reg = <0x01c20050 0x4>; @@ -47,7 +47,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "axi"; >>> + }; >>> + ->>> + ahb1: ahb1_clk at 01c20054 { +>>> + ahb1: ahb1_clk@01c20054 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >>> + reg = <0x01c20054 0x4>; @@ -55,7 +55,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "ahb1"; >>> + }; >>> + ->>> + ahb2: ahb2_clk at 01c2005c { +>>> + ahb2: ahb2_clk@01c2005c { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >>> + reg = <0x01c2005c 0x4>; @@ -63,7 +63,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "ahb2"; >>> + }; >>> + ->>> + apb1: apb1_clk at 01c20054 { +>>> + apb1: apb1_clk@01c20054 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-apb0-clk"; >>> + reg = <0x01c20054 0x4>; @@ -71,7 +71,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "apb1"; >>> + }; >>> + ->>> + apb2: apb2_clk at 01c20058 { +>>> + apb2: apb2_clk@01c20058 { >>> + #clock-cells = <0>; >>> + compatible = "allwinner,sun4i-a10-apb1-clk"; >>> + reg = <0x01c20058 0x4>; @@ -79,7 +79,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + clock-output-names = "apb2"; >>> + }; >>> + ->>> + bus_gates: clk at 01c20060 { +>>> + bus_gates: clk@01c20060 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,a64-bus-gates-clk", >>> + "allwinner,sunxi-multi-bus-gates-clk"; @@ -146,7 +146,7 @@ http://www.spinics.net/lists/linux-clk/msg06242.html >>> + }; >>> + }; >>> + ->>> + mmc0_clk: clk at 01c20088 { +>>> + mmc0_clk: clk@01c20088 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> @@ -178,7 +178,7 @@ Maximes work. >>> + "mmc0_sample"; >>> + }; >>> + ->>> + mmc1_clk: clk at 01c2008c { +>>> + mmc1_clk: clk@01c2008c { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun4i-a10-mmc-clk"; >>> + reg = <0x01c2008c 0x4>; @@ -188,7 +188,7 @@ Maximes work. >>> + "mmc1_sample"; >>> + }; >>> + ->>> + mmc2_clk: clk at 01c20090 { +>>> + mmc2_clk: clk@01c20090 { >>> + #clock-cells = <1>; >>> + compatible = "allwinner,sun4i-a10-mmc-clk"; >>> + reg = <0x01c20090 0x4>; @@ -214,7 +214,7 @@ Maximes work. >>> + #size-cells = <1>; >>> + ranges; >>> + ->>> + mmc0: mmc at 01c0f000 { +>>> + mmc0: mmc@01c0f000 { >>> + compatible = "allwinner,sun5i-a13-mmc"; >>> + reg = <0x01c0f000 0x1000>; >>> + clocks = <&bus_gates 8>, diff --git a/a/content_digest b/N2/content_digest index 314a930..6d5bd86 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,10 +2,24 @@ "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" "ref\056B0D83E.5090604@gmail.com\0" "ref\056B0DD67.3060802@arm.com\0" - "From\0jenskuske@gmail.com (Jens Kuske)\0" - "Subject\0[linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "From\0Jens Kuske <jenskuske@gmail.com>\0" + "Subject\0Re: [linux-sunxi] [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Tue, 2 Feb 2016 18:40:25 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0andre.przywara@arm.com\0" + "Cc\0Maxime Ripard <maxime.ripard@free-electrons.com>" + Chen-Yu Tsai <wens@csie.org> + linux-sunxi@googlegroups.com + Arnd Bergmann <arnd@arndb.de> + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Hi,\n" @@ -40,7 +54,7 @@ "\n" ">\n" ">>> +\n" - ">>> +\t\tcpu: cpu_clk at 01c20050 {\n" + ">>> +\t\tcpu: cpu_clk@01c20050 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">>> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -49,7 +63,7 @@ ">>> +\t\t\tcritical-clocks = <0>;\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\taxi: axi_clk at 01c20050 {\n" + ">>> +\t\taxi: axi_clk@01c20050 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">>> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -57,7 +71,7 @@ ">>> +\t\t\tclock-output-names = \"axi\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tahb1: ahb1_clk at 01c20054 {\n" + ">>> +\t\tahb1: ahb1_clk@01c20054 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">>> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -65,7 +79,7 @@ ">>> +\t\t\tclock-output-names = \"ahb1\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tahb2: ahb2_clk at 01c2005c {\n" + ">>> +\t\tahb2: ahb2_clk@01c2005c {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">>> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -73,7 +87,7 @@ ">>> +\t\t\tclock-output-names = \"ahb2\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tapb1: apb1_clk at 01c20054 {\n" + ">>> +\t\tapb1: apb1_clk@01c20054 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">>> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -81,7 +95,7 @@ ">>> +\t\t\tclock-output-names = \"apb1\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tapb2: apb2_clk at 01c20058 {\n" + ">>> +\t\tapb2: apb2_clk@01c20058 {\n" ">>> +\t\t\t#clock-cells = <0>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">>> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -89,7 +103,7 @@ ">>> +\t\t\tclock-output-names = \"apb2\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tbus_gates: clk at 01c20060 {\n" + ">>> +\t\tbus_gates: clk@01c20060 {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" ">>> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -156,7 +170,7 @@ ">>> +\t\t\t};\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tmmc0_clk: clk at 01c20088 {\n" + ">>> +\t\tmmc0_clk: clk@01c20088 {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">>\n" @@ -188,7 +202,7 @@ ">>> +\t\t\t\t\t \"mmc0_sample\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tmmc1_clk: clk at 01c2008c {\n" + ">>> +\t\tmmc1_clk: clk@01c2008c {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">>> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -198,7 +212,7 @@ ">>> +\t\t\t\t\t \"mmc1_sample\";\n" ">>> +\t\t};\n" ">>> +\n" - ">>> +\t\tmmc2_clk: clk at 01c20090 {\n" + ">>> +\t\tmmc2_clk: clk@01c20090 {\n" ">>> +\t\t\t#clock-cells = <1>;\n" ">>> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">>> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -224,7 +238,7 @@ ">>> +\t\t#size-cells = <1>;\n" ">>> +\t\tranges;\n" ">>> +\n" - ">>> +\t\tmmc0: mmc at 01c0f000 {\n" + ">>> +\t\tmmc0: mmc@01c0f000 {\n" ">>> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">>> +\t\t\treg = <0x01c0f000 0x1000>;\n" ">>> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -263,4 +277,4 @@ "\n" Jens -1a11af047a143589ca60ac41ae13e19caa1880524802f8bb995cbc7331ce2055 +6b150b8a748188f9f3efcb1ad4b130ff5179b4467ffac518fe11cfe30455e1ee
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