Re: [PATCH 2/2] drm/i915/dp: reduce missing TPS3 support errors to debug logging

["Thulasimani, Sivakumar" <sivakumar.thulasimani@intel.com>]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 2/5/2016 3:46 PM, Jani Nikula wrote:
> Per spec, TPS3 support is mandatory for downstream devices that support
> HBR2. We've therefore logged errors on HBR2 without TPS3 since
>
> commit 1da7d7131c35cde83f1bab8ec732b57b69bef814
> Author: Jani Nikula <jani.nikula@intel.com>
> Date:   Thu Sep 3 11:16:08 2015 +0300
>
>      drm/i915: ignore link rate in TPS3 selection
>
> However, it seems there are real world devices out there that just
> aren't spec compliant, and still work at HBR2 using TPS2. So reduce the
> error message to debug logging.
>
> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com>
> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92932
> Fixes: 1da7d7131c35 ("drm/i915: ignore link rate in TPS3 selection")
> Cc: drm-intel-fixes@lists.freedesktop.org
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_dp_link_training.c | 20 ++++++++++++++------
>   1 file changed, 14 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_link_training.c b/drivers/gpu/drm/i915/intel_dp_link_training.c
> index 83e667b92fda..0b8eefc2acc5 100644
> --- a/drivers/gpu/drm/i915/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/intel_dp_link_training.c
> @@ -222,19 +222,27 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
>   static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
>   {
>   	u32 training_pattern = DP_TRAINING_PATTERN_2;
> +	bool source_tps3, sink_tps3;
>   
>   	/*
>   	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
> -	 * also mandatory for downstream devices that support HBR2.
> +	 * also mandatory for downstream devices that support HBR2. However, not
> +	 * all sinks follow the spec.
>   	 *
>   	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
> -	 * supported but still not enabled.
> +	 * supported in source but still not enabled.
>   	 */
> -	if (intel_dp_source_supports_hbr2(intel_dp) &&
> -	    drm_dp_tps3_supported(intel_dp->dpcd))
> +	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
> +	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
> +
> +	if (source_tps3 && sink_tps3) {
>   		training_pattern = DP_TRAINING_PATTERN_3;
> -	else if (intel_dp->link_rate == 540000)
> -		DRM_ERROR("5.4 Gbps link rate without HBR2/TPS3 support\n");
> +	} else if (intel_dp->link_rate == 540000) {
> +		if (!source_tps3)
> +			DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
> +		if (!sink_tps3)
> +			DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
> +	}
>   
>   	return training_pattern;
>   }

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