From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brijesh Singh Subject: Re: [PATCH v2] ata: add AMD Seattle platform driver Date: Fri, 5 Feb 2016 11:23:23 -0600 Message-ID: <56B4DA8B.2050609@amd.com> References: <1452789071-4090-1-git-send-email-brijesh.singh@amd.com> <4743985.XZ7D12RurV@wuerfel> <56B0F786.9010504@amd.com> <3134806.iILWebdeN8@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-bl2on0068.outbound.protection.outlook.com ([65.55.169.68]:60220 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752669AbcBER0B (ORCPT ); Fri, 5 Feb 2016 12:26:01 -0500 In-Reply-To: <3134806.iILWebdeN8@wuerfel> Sender: linux-ide-owner@vger.kernel.org List-Id: linux-ide@vger.kernel.org To: Arnd Bergmann Cc: brijesh.singh@amd.com, Tejun Heo , linux-kernel@vger.kernel.org, hdegoede@redhat.com, linux-ide@vger.kernel.org, Graeme Gregory Hi, >> } >> >> Windows driver folks were okay to look at second resource field to map the SGPIO register and program the >> registers to blink the LEDs. I think as per ACPI spec, its legal to pass more than one block in resource >> template and since AML method is not mandatory for non standard enclosure management hence its entirely >> possible that some BIOS vendors may not implement it at all. But if they implement and decide >> to expose either AML method or register map but not both then Windows driver may break. > > I don't have access to the Windows source code. Is this in the > architecture-independent part of their kernel, or only done on ARM64? > How do they decide what the second memory range is for? > > If this is now a de-facto extension to the PCI_CLASS_STORAGE_SATA_AHCI binding, > it should probably be put into the next version of the AHCI spec, and then > there is no problem using it. > I don't have Windows code either and do not know the implementation details. I was told by the AMD folks working on Windows drivers for Seattle that they do not need any changes in BIOS DSDT to get the LEDs blinking. This is not a de-facto extension of SATA_AHCI binding, you can call this method as a SoC hack to support the LEDs. We are working with whatever BIOS is already available to enable the LEDs blinking. > > Arnd > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755855AbcBER0F (ORCPT ); Fri, 5 Feb 2016 12:26:05 -0500 Received: from mail-bl2on0068.outbound.protection.outlook.com ([65.55.169.68]:60220 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752669AbcBER0B (ORCPT ); Fri, 5 Feb 2016 12:26:01 -0500 Authentication-Results: spf=none (sender IP is 165.204.84.222) smtp.mailfrom=amd.com; arndb.de; dkim=none (message not signed) header.d=none;arndb.de; dmarc=permerror action=none header.from=amd.com; X-WSS-ID: 0O234F5-08-01N-02 X-M-MSG: Subject: Re: [PATCH v2] ata: add AMD Seattle platform driver To: Arnd Bergmann References: <1452789071-4090-1-git-send-email-brijesh.singh@amd.com> <4743985.XZ7D12RurV@wuerfel> <56B0F786.9010504@amd.com> <3134806.iILWebdeN8@wuerfel> CC: , Tejun Heo , , , , Graeme Gregory From: Brijesh Singh Message-ID: <56B4DA8B.2050609@amd.com> Date: Fri, 5 Feb 2016 11:23:23 -0600 User-Agent: Mozilla/5.0 (X11; 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I think as per ACPI spec, its legal to pass more than one block in resource >> template and since AML method is not mandatory for non standard enclosure management hence its entirely >> possible that some BIOS vendors may not implement it at all. But if they implement and decide >> to expose either AML method or register map but not both then Windows driver may break. > > I don't have access to the Windows source code. Is this in the > architecture-independent part of their kernel, or only done on ARM64? > How do they decide what the second memory range is for? > > If this is now a de-facto extension to the PCI_CLASS_STORAGE_SATA_AHCI binding, > it should probably be put into the next version of the AHCI spec, and then > there is no problem using it. > I don't have Windows code either and do not know the implementation details. I was told by the AMD folks working on Windows drivers for Seattle that they do not need any changes in BIOS DSDT to get the LEDs blinking. This is not a de-facto extension of SATA_AHCI binding, you can call this method as a SoC hack to support the LEDs. We are working with whatever BIOS is already available to enable the LEDs blinking. > > Arnd >