diff for duplicates of <56B4E2FB.3050703@arm.com> diff --git a/a/1.txt b/N1/1.txt index 84ad431..0db4c3a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -97,7 +97,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > @@ -201,11 +201,11 @@ > }; > -> pll6: clk@01c20028 { +> pll6: clk at 01c20028 { > - #clock-cells = <1>; > + #clock-cells = <0>; > compatible = "allwinner,sun6i-a31-pll6-clk"; @@ -107,7 +107,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > + clock-output-names = "pll6"; > }; > -> cpu: cpu@01c20050 { +> cpu: cpu at 01c20050 { > @@ -235,7 +235,7 @@ > #clock-cells = <0>; > compatible = "allwinner,sun6i-a31-ahb1-clk"; @@ -125,7 +125,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > + assigned-clock-parents = <&pll6>; > }; > -> ahb1_gates: clk@01c20060 { +> ahb1_gates: clk at 01c20060 { > @@ -307,7 +307,7 @@ > #clock-cells = <0>; > compatible = "allwinner,sun4i-a10-apb1-clk"; @@ -243,7 +243,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > @@ -129,11 +129,20 @@ > }; > -> pll6: clk@01c20028 { +> pll6: clk at 01c20028 { > - #clock-cells = <1>; > + #clock-cells = <0>; > compatible = "allwinner,sun6i-a31-pll6-clk"; @@ -262,7 +262,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > + clock-output-names = "pll6-2x"; > }; > -> cpu: cpu_clk@01c20050 { +> cpu: cpu_clk at 01c20050 { > @@ -163,7 +172,7 @@ > #clock-cells = <0>; > compatible = "allwinner,sun6i-a31-ahb1-clk"; @@ -350,7 +350,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > @@ -121,11 +121,11 @@ > }; > -> pll6: clk@01c20028 { +> pll6: clk at 01c20028 { > - #clock-cells = <1>; > + #clock-cells = <0>; > compatible = "allwinner,sun6i-a31-pll6-clk"; @@ -384,7 +384,7 @@ http://lists.infradead.org/pipermail/linux-arm-kernel/2016-February/405104.html > + clock-output-names = "pll6-2x"; > + }; > + -> + pll8: clk@01c20044 { +> + pll8: clk at 01c20044 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20044 0x4>; diff --git a/a/content_digest b/N1/content_digest index a37a628..1d650b2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,22 +1,8 @@ "ref\01454358000-13594-1-git-send-email-maxime.ripard@free-electrons.com\0" - "From\0Andre Przywara <andre.przywara@arm.com>\0" - "Subject\0Re: [PATCH v4] clk: sunxi: Refactor A31 PLL6 so that it can be reused\0" + "From\0andre.przywara@arm.com (Andre Przywara)\0" + "Subject\0[PATCH v4] clk: sunxi: Refactor A31 PLL6 so that it can be reused\0" "Date\0Fri, 5 Feb 2016 17:59:23 +0000\0" - "To\0Maxime Ripard <maxime.ripard@free-electrons.com>" - " Chen-Yu Tsai <wens@csie.org>\0" - "Cc\0Jean-Francois Moine <moinejf@free.fr>" - Vishnu Patekar <vishnupatekar0510@gmail.com> - Mike Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - Hans de Goede <hdegoede@redhat.com> - Jens Kuske <jenskuske@gmail.com> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - Mark Rutland <mark.rutland@arm.com> - Rob Herring <rob.herring@linaro.org> - Frank Rowand <frowand.list@gmail.com> - Grant Likely <grant.likely@linaro.org> - " devicetree@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Maxime,\n" @@ -118,7 +104,7 @@ "> @@ -201,11 +201,11 @@\n" "> \t\t};\n" "> \n" - "> \t\tpll6: clk@01c20028 {\n" + "> \t\tpll6: clk at 01c20028 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" @@ -128,7 +114,7 @@ "> +\t\t\tclock-output-names = \"pll6\";\n" "> \t\t};\n" "> \n" - "> \t\tcpu: cpu@01c20050 {\n" + "> \t\tcpu: cpu at 01c20050 {\n" "> @@ -235,7 +235,7 @@\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" @@ -146,7 +132,7 @@ "> +\t\t\tassigned-clock-parents = <&pll6>;\n" "> \t\t};\n" "> \n" - "> \t\tahb1_gates: clk@01c20060 {\n" + "> \t\tahb1_gates: clk at 01c20060 {\n" "> @@ -307,7 +307,7 @@\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" @@ -264,7 +250,7 @@ "> @@ -129,11 +129,20 @@\n" "> \t\t};\n" "> \n" - "> \t\tpll6: clk@01c20028 {\n" + "> \t\tpll6: clk at 01c20028 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" @@ -283,7 +269,7 @@ "> +\t\t\tclock-output-names = \"pll6-2x\";\n" "> \t\t};\n" "> \n" - "> \t\tcpu: cpu_clk@01c20050 {\n" + "> \t\tcpu: cpu_clk at 01c20050 {\n" "> @@ -163,7 +172,7 @@\n" "> \t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" @@ -371,7 +357,7 @@ "> @@ -121,11 +121,11 @@\n" "> \t\t};\n" "> \n" - "> \t\tpll6: clk@01c20028 {\n" + "> \t\tpll6: clk at 01c20028 {\n" "> -\t\t\t#clock-cells = <1>;\n" "> +\t\t\t#clock-cells = <0>;\n" "> \t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" @@ -405,7 +391,7 @@ "> +\t\t\tclock-output-names = \"pll6-2x\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll8: clk@01c20044 {\n" + "> +\t\tpll8: clk at 01c20044 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20044 0x4>;\n" @@ -554,4 +540,4 @@ "> \n" > -079ed6024c2ead401fcf781d9a69251a4424367d5c661f684c428e834498f510 +abb0ce8e4a9d3c5f4c4fd02e7617ce32e91300a22d65cfff73271a0d74ed8114
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