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[46.188.121.154]) by smtp.googlemail.com with ESMTPSA id l8sm2992145lfe.24.2016.02.06.10.24.28 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 06 Feb 2016 10:24:28 -0800 (PST) From: Sergey Fedorov To: Peter Maydell , qemu-devel@nongnu.org References: <1454683067-16001-1-git-send-email-peter.maydell@linaro.org> <1454683067-16001-3-git-send-email-peter.maydell@linaro.org> Message-ID: <56B63A5B.6020400@gmail.com> Date: Sat, 6 Feb 2016 21:24:27 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1454683067-16001-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c04::243 Cc: qemu-arm@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH 2/3] target-arm: Fix IL bit reported for Thumb coprocessor traps X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: Yrd2n+i85uUv On 05.02.2016 17:37, Peter Maydell wrote: > All Thumb coprocessor instructions are 32 bits, so the IL > bit in the syndrome register should be set. Pass false to the > syn_* function's is_16bit argument rather than s->thumb > so we report the correct IL bit. > > Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov > --- > target-arm/translate.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 3ec758a..10792e8 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7184,19 +7184,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) > case 14: > if (is64) { > syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, > - isread, s->thumb); > + isread, false); > } else { > syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, > - rt, isread, s->thumb); > + rt, isread, false); > } > break; > case 15: > if (is64) { > syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, > - isread, s->thumb); > + isread, false); > } else { > syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, > - rt, isread, s->thumb); > + rt, isread, false); > } > break; > default: From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44150) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aS7X7-0001sH-Gd for qemu-devel@nongnu.org; Sat, 06 Feb 2016 13:24:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aS7X6-0007yw-Jc for qemu-devel@nongnu.org; Sat, 06 Feb 2016 13:24:33 -0500 From: Sergey Fedorov References: <1454683067-16001-1-git-send-email-peter.maydell@linaro.org> <1454683067-16001-3-git-send-email-peter.maydell@linaro.org> Message-ID: <56B63A5B.6020400@gmail.com> Date: Sat, 6 Feb 2016 21:24:27 +0300 MIME-Version: 1.0 In-Reply-To: <1454683067-16001-3-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/3] target-arm: Fix IL bit reported for Thumb coprocessor traps List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, patches@linaro.org On 05.02.2016 17:37, Peter Maydell wrote: > All Thumb coprocessor instructions are 32 bits, so the IL > bit in the syndrome register should be set. Pass false to the > syn_* function's is_16bit argument rather than s->thumb > so we report the correct IL bit. > > Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov > --- > target-arm/translate.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 3ec758a..10792e8 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7184,19 +7184,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) > case 14: > if (is64) { > syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, > - isread, s->thumb); > + isread, false); > } else { > syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, > - rt, isread, s->thumb); > + rt, isread, false); > } > break; > case 15: > if (is64) { > syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, > - isread, s->thumb); > + isread, false); > } else { > syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, > - rt, isread, s->thumb); > + rt, isread, false); > } > break; > default: