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[46.188.121.154]) by smtp.googlemail.com with ESMTPSA id h75sm2912266lfi.2.2016.02.06.10.25.06 (version=TLSv1/SSLv3 cipher=OTHER); Sat, 06 Feb 2016 10:25:06 -0800 (PST) From: Sergey Fedorov To: Peter Maydell , qemu-devel@nongnu.org References: <1454683067-16001-1-git-send-email-peter.maydell@linaro.org> <1454683067-16001-2-git-send-email-peter.maydell@linaro.org> Message-ID: <56B63A82.6060508@gmail.com> Date: Sat, 6 Feb 2016 21:25:06 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1454683067-16001-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:4010:c04::241 Cc: qemu-arm@nongnu.org, patches@linaro.org Subject: Re: [Qemu-arm] [PATCH 1/3] target-arm: Correct misleading 'is_thumb' syn_* parameter names X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: Cc2f9Zc3cDLY On 05.02.2016 17:37, Peter Maydell wrote: > In syndrome register values, the IL bit indicates the instruction > length, and is 1 for 4-byte instructions and 0 for 2-byte > instructions. All A64 and A32 instructions are 4-byte, but > Thumb instructions may be either 2 or 4 bytes long. Unfortunately > we named the parameter to the syn_* functions for constructing > syndromes "is_thumb", which falsely implies that it should be > set for all Thumb instructions, rather than only the 16-bit ones. > Fix the functions to name the parameter 'is_16bit' instead. > > Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov > --- > target-arm/internals.h | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/target-arm/internals.h b/target-arm/internals.h > index d226bbe..a648c1e 100644 > --- a/target-arm/internals.h > +++ b/target-arm/internals.h > @@ -270,10 +270,10 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16) > return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); > } > > -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb) > +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) > { > return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) > - | (is_thumb ? 0 : ARM_EL_IL); > + | (is_16bit ? 0 : ARM_EL_IL); > } > > static inline uint32_t syn_aa32_hvc(uint32_t imm16) > @@ -291,10 +291,10 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16) > return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); > } > > -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb) > +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) > { > return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) > - | (is_thumb ? 0 : ARM_EL_IL); > + | (is_16bit ? 0 : ARM_EL_IL); > } > > static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, > @@ -308,48 +308,48 @@ static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, > > static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, > int crn, int crm, int rt, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) > | (crn << 10) | (rt << 5) | (crm << 1) | isread; > } > > static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, > int crn, int crm, int rt, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) > | (crn << 10) | (rt << 5) | (crm << 1) | isread; > } > > static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, > int rt, int rt2, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc1 << 16) > | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; > } > > static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, > int rt, int rt2, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc1 << 16) > | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; > } > > -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb) > +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) > { > return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20); > } > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aS7Xm-000323-Kz for qemu-devel@nongnu.org; Sat, 06 Feb 2016 13:25:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aS7Xl-00087j-Bo for qemu-devel@nongnu.org; Sat, 06 Feb 2016 13:25:14 -0500 From: Sergey Fedorov References: <1454683067-16001-1-git-send-email-peter.maydell@linaro.org> <1454683067-16001-2-git-send-email-peter.maydell@linaro.org> Message-ID: <56B63A82.6060508@gmail.com> Date: Sat, 6 Feb 2016 21:25:06 +0300 MIME-Version: 1.0 In-Reply-To: <1454683067-16001-2-git-send-email-peter.maydell@linaro.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 1/3] target-arm: Correct misleading 'is_thumb' syn_* parameter names List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, patches@linaro.org On 05.02.2016 17:37, Peter Maydell wrote: > In syndrome register values, the IL bit indicates the instruction > length, and is 1 for 4-byte instructions and 0 for 2-byte > instructions. All A64 and A32 instructions are 4-byte, but > Thumb instructions may be either 2 or 4 bytes long. Unfortunately > we named the parameter to the syn_* functions for constructing > syndromes "is_thumb", which falsely implies that it should be > set for all Thumb instructions, rather than only the 16-bit ones. > Fix the functions to name the parameter 'is_16bit' instead. > > Signed-off-by: Peter Maydell Reviewed-by: Sergey Fedorov > --- > target-arm/internals.h | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/target-arm/internals.h b/target-arm/internals.h > index d226bbe..a648c1e 100644 > --- a/target-arm/internals.h > +++ b/target-arm/internals.h > @@ -270,10 +270,10 @@ static inline uint32_t syn_aa64_smc(uint32_t imm16) > return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); > } > > -static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb) > +static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit) > { > return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) > - | (is_thumb ? 0 : ARM_EL_IL); > + | (is_16bit ? 0 : ARM_EL_IL); > } > > static inline uint32_t syn_aa32_hvc(uint32_t imm16) > @@ -291,10 +291,10 @@ static inline uint32_t syn_aa64_bkpt(uint32_t imm16) > return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff); > } > > -static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb) > +static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit) > { > return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff) > - | (is_thumb ? 0 : ARM_EL_IL); > + | (is_16bit ? 0 : ARM_EL_IL); > } > > static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, > @@ -308,48 +308,48 @@ static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2, > > static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, > int crn, int crm, int rt, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) > | (crn << 10) | (rt << 5) | (crm << 1) | isread; > } > > static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, > int crn, int crm, int rt, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) > | (crn << 10) | (rt << 5) | (crm << 1) | isread; > } > > static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, > int rt, int rt2, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc1 << 16) > | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; > } > > static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, > int rt, int rt2, int isread, > - bool is_thumb) > + bool is_16bit) > { > return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20) | (opc1 << 16) > | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; > } > > -static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb) > +static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) > { > return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT) > - | (is_thumb ? 0 : ARM_EL_IL) > + | (is_16bit ? 0 : ARM_EL_IL) > | (cv << 24) | (cond << 20); > } >