From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH v2] arm64: dts: r8a7795: Add L2 cache-controller nodes To: Geert Uytterhoeven , Dirk Behme References: <1452953856-5146-1-git-send-email-dirk.behme@gmail.com> <56B2370D.2010102@gmail.com> <20160205095758.GE16556@verge.net.au> CC: Simon Horman , Geert Uytterhoeven , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , From: Dirk Behme Message-ID: <56B857AC.4090701@de.bosch.com> Date: Mon, 8 Feb 2016 09:54:04 +0100 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Sender: devicetree-owner@vger.kernel.org List-ID: On 08.02.2016 09:42, Geert Uytterhoeven wrote: > Hi Dirk, > > On Fri, Feb 5, 2016 at 10:57 AM, Simon Horman wrote: >> On Wed, Feb 03, 2016 at 06:21:17PM +0100, Dirk Behme wrote: >>> On 16.01.2016 15:17, Dirk Behme wrote: >>>> From: Geert Uytterhoeven >>>> >>>> Add device nodes for the L2 caches, and link the CPU node to its L2 >>>> cache node. >>>> >>>> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as >>>> 128 KiB x 16 ways). >>>> >>>> Signed-off-by: Geert Uytterhoeven >>>> Signed-off-by: Dirk Behme >> >> [snip] >> >>> Any further comments to this? If not, could this be applied? >> >> Sorry for the delay. >> >> This looks good; I have queued it up. >> >> It should appear in the next (and devel) branches of my renesas tree soon. >> And in linux-next whenever it includes my updated next branch. > > So you not only dropped the (controversial) timing related properties, but > in addition: > > + cache-unified; > + cache-level = <2>; > > At least the "cache-level" property is marked as required in ePAPR. > For "cache-unified", the wording is not that strict in ePAPR, but that property > depends on being a unified cache in the first place. > > So I think these two properties should be re-added. If I remember correctly, first, these entries are not used at all on ARMv8. And second, I think it was mentioned that we therefore want to drop them: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394936.html https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/Documentation/devicetree/bindings/arm/l2c2x0.txt?id=0bed4b7aa02c06e05121875dc443295d55b9d91d Best regards Dirk From mboxrd@z Thu Jan 1 00:00:00 1970 From: dirk.behme@de.bosch.com (Dirk Behme) Date: Mon, 8 Feb 2016 09:54:04 +0100 Subject: [PATCH v2] arm64: dts: r8a7795: Add L2 cache-controller nodes In-Reply-To: References: <1452953856-5146-1-git-send-email-dirk.behme@gmail.com> <56B2370D.2010102@gmail.com> <20160205095758.GE16556@verge.net.au> Message-ID: <56B857AC.4090701@de.bosch.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 08.02.2016 09:42, Geert Uytterhoeven wrote: > Hi Dirk, > > On Fri, Feb 5, 2016 at 10:57 AM, Simon Horman wrote: >> On Wed, Feb 03, 2016 at 06:21:17PM +0100, Dirk Behme wrote: >>> On 16.01.2016 15:17, Dirk Behme wrote: >>>> From: Geert Uytterhoeven >>>> >>>> Add device nodes for the L2 caches, and link the CPU node to its L2 >>>> cache node. >>>> >>>> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as >>>> 128 KiB x 16 ways). >>>> >>>> Signed-off-by: Geert Uytterhoeven >>>> Signed-off-by: Dirk Behme >> >> [snip] >> >>> Any further comments to this? If not, could this be applied? >> >> Sorry for the delay. >> >> This looks good; I have queued it up. >> >> It should appear in the next (and devel) branches of my renesas tree soon. >> And in linux-next whenever it includes my updated next branch. > > So you not only dropped the (controversial) timing related properties, but > in addition: > > + cache-unified; > + cache-level = <2>; > > At least the "cache-level" property is marked as required in ePAPR. > For "cache-unified", the wording is not that strict in ePAPR, but that property > depends on being a unified cache in the first place. > > So I think these two properties should be re-added. If I remember correctly, first, these entries are not used at all on ARMv8. And second, I think it was mentioned that we therefore want to drop them: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394936.html https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/Documentation/devicetree/bindings/arm/l2c2x0.txt?id=0bed4b7aa02c06e05121875dc443295d55b9d91d Best regards Dirk From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dirk Behme Subject: Re: [PATCH v2] arm64: dts: r8a7795: Add L2 cache-controller nodes Date: Mon, 8 Feb 2016 09:54:04 +0100 Message-ID: <56B857AC.4090701@de.bosch.com> References: <1452953856-5146-1-git-send-email-dirk.behme@gmail.com> <56B2370D.2010102@gmail.com> <20160205095758.GE16556@verge.net.au> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Geert Uytterhoeven , Dirk Behme Cc: Simon Horman , Geert Uytterhoeven , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On 08.02.2016 09:42, Geert Uytterhoeven wrote: > Hi Dirk, > > On Fri, Feb 5, 2016 at 10:57 AM, Simon Horman wrote: >> On Wed, Feb 03, 2016 at 06:21:17PM +0100, Dirk Behme wrote: >>> On 16.01.2016 15:17, Dirk Behme wrote: >>>> From: Geert Uytterhoeven >>>> >>>> Add device nodes for the L2 caches, and link the CPU node to its L2 >>>> cache node. >>>> >>>> The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as >>>> 128 KiB x 16 ways). >>>> >>>> Signed-off-by: Geert Uytterhoeven >>>> Signed-off-by: Dirk Behme >> >> [snip] >> >>> Any further comments to this? If not, could this be applied? >> >> Sorry for the delay. >> >> This looks good; I have queued it up. >> >> It should appear in the next (and devel) branches of my renesas tree soon. >> And in linux-next whenever it includes my updated next branch. > > So you not only dropped the (controversial) timing related properties, but > in addition: > > + cache-unified; > + cache-level = <2>; > > At least the "cache-level" property is marked as required in ePAPR. > For "cache-unified", the wording is not that strict in ePAPR, but that property > depends on being a unified cache in the first place. > > So I think these two properties should be re-added. If I remember correctly, first, these entries are not used at all on ARMv8. And second, I think it was mentioned that we therefore want to drop them: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/394936.html https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/Documentation/devicetree/bindings/arm/l2c2x0.txt?id=0bed4b7aa02c06e05121875dc443295d55b9d91d Best regards Dirk -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html