diff for duplicates of <56B8630B.8060608@arm.com> diff --git a/a/1.txt b/N1/1.txt index 26dc5ec..afe45f3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -124,28 +124,28 @@ Sure. >> + #address-cells = <1>; >> + #size-cells = <0>; >> + ->> + cpu at 0 { +>> + cpu@0 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <0>; >> + enable-method = "psci"; >> + }; >> + ->> + cpu at 1 { +>> + cpu@1 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <1>; >> + enable-method = "psci"; >> + }; >> + ->> + cpu at 2 { +>> + cpu@2 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <2>; >> + enable-method = "psci"; >> + }; >> + ->> + cpu at 3 { +>> + cpu@3 { >> + compatible = "arm,cortex-a53", "arm,armv8"; >> + device_type = "cpu"; >> + reg = <3>; @@ -213,7 +213,7 @@ patching easier). >> + clock-output-names = "osc32k"; >> + }; >> + ->> + pll1: clk at 01c20000 { +>> + pll1: clk@01c20000 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-a23-pll1-clk"; >> + reg = <0x01c20000 0x4>; @@ -221,7 +221,7 @@ patching easier). >> + clock-output-names = "pll1"; >> + }; >> + ->> + pll6: clk at 01c20028 { +>> + pll6: clk@01c20028 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun6i-a31-pll6-clk"; >> + reg = <0x01c20028 0x4>; @@ -253,7 +253,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + clock-output-names = "pll8"; >> + }; >> + ->> + cpu: cpu_clk at 01c20050 { +>> + cpu: cpu_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-cpu-clk"; >> + reg = <0x01c20050 0x4>; @@ -262,7 +262,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + critical-clocks = <0>; >> + }; >> + ->> + axi: axi_clk at 01c20050 { +>> + axi: axi_clk@01c20050 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-axi-clk"; >> + reg = <0x01c20050 0x4>; @@ -270,7 +270,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + clock-output-names = "axi"; >> + }; >> + ->> + ahb1: ahb1_clk at 01c20054 { +>> + ahb1: ahb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun6i-a31-ahb1-clk"; >> + reg = <0x01c20054 0x4>; @@ -278,7 +278,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + clock-output-names = "ahb1"; >> + }; >> + ->> + ahb2: ahb2_clk at 01c2005c { +>> + ahb2: ahb2_clk@01c2005c { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun8i-h3-ahb2-clk"; >> + reg = <0x01c2005c 0x4>; @@ -286,7 +286,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + clock-output-names = "ahb2"; >> + }; >> + ->> + apb1: apb1_clk at 01c20054 { +>> + apb1: apb1_clk@01c20054 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb0-clk"; >> + reg = <0x01c20054 0x4>; @@ -294,7 +294,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + clock-output-names = "apb1"; >> + }; >> + ->> + apb2: apb2_clk at 01c20058 { +>> + apb2: apb2_clk@01c20058 { >> + #clock-cells = <0>; >> + compatible = "allwinner,sun4i-a10-apb1-clk"; >> + reg = <0x01c20058 0x4>; @@ -302,7 +302,7 @@ Would be happy to adapt to this, but we should sort this approach out >> + clock-output-names = "apb2"; >> + }; >> + ->> + bus_gates: clk at 01c20060 { +>> + bus_gates: clk@01c20060 { >> + #clock-cells = <1>; >> + compatible = "allwinner,a64-bus-gates-clk", >> + "allwinner,sunxi-multi-bus-gates-clk"; @@ -459,7 +459,7 @@ I really rather would avoid doing this. I would appreciate if other people could comment on this. > ->> + mmc0_clk: clk at 01c20088 { +>> + mmc0_clk: clk@01c20088 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20088 0x4>; @@ -469,7 +469,7 @@ I would appreciate if other people could comment on this. >> + "mmc0_sample"; >> + }; >> + ->> + mmc1_clk: clk at 01c2008c { +>> + mmc1_clk: clk@01c2008c { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c2008c 0x4>; @@ -479,7 +479,7 @@ I would appreciate if other people could comment on this. >> + "mmc1_sample"; >> + }; >> + ->> + mmc2_clk: clk at 01c20090 { +>> + mmc2_clk: clk@01c20090 { >> + #clock-cells = <1>; >> + compatible = "allwinner,sun4i-a10-mmc-clk"; >> + reg = <0x01c20090 0x4>; @@ -505,7 +505,7 @@ I would appreciate if other people could comment on this. >> + #size-cells = <1>; >> + ranges; >> + ->> + mmc0: mmc at 01c0f000 { +>> + mmc0: mmc@01c0f000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c0f000 0x1000>; >> + clocks = <&bus_gates 8>, @@ -524,7 +524,7 @@ I would appreciate if other people could comment on this. >> + #size-cells = <0>; >> + }; >> + ->> + mmc1: mmc at 01c10000 { +>> + mmc1: mmc@01c10000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c10000 0x1000>; >> + clocks = <&bus_gates 9>, @@ -543,7 +543,7 @@ I would appreciate if other people could comment on this. >> + #size-cells = <0>; >> + }; >> + ->> + mmc2: mmc at 01c11000 { +>> + mmc2: mmc@01c11000 { >> + compatible = "allwinner,sun5i-a13-mmc"; >> + reg = <0x01c11000 0x1000>; >> + clocks = <&bus_gates 10>, @@ -562,7 +562,7 @@ I would appreciate if other people could comment on this. >> + #size-cells = <0>; >> + }; >> + ->> + pio: pinctrl at 01c20800 { +>> + pio: pinctrl@01c20800 { >> + compatible = "allwinner,a64-pinctrl"; >> + reg = <0x01c20800 0x400>; >> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -574,42 +574,42 @@ I would appreciate if other people could comment on this. >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + ->> + uart0_pins_a: uart0 at 0 { +>> + uart0_pins_a: uart0@0 { >> + allwinner,pins = "PB8", "PB9"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + uart0_pins_b: uart0 at 1 { +>> + uart0_pins_b: uart0@1 { >> + allwinner,pins = "PF2", "PF3"; >> + allwinner,function = "uart0"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + uart1_pins: uart1 at 0 { +>> + uart1_pins: uart1@0 { >> + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; >> + allwinner,function = "uart1"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + uart2_pins: uart2 at 0 { +>> + uart2_pins: uart2@0 { >> + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; >> + allwinner,function = "uart2"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + uart3_pins_a: uart3 at 0 { +>> + uart3_pins_a: uart3@0 { >> + allwinner,pins = "PD0", "PD1"; >> + allwinner,function = "uart3"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; >> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; >> + }; >> + ->> + uart3_pins_b: uart3 at 1 { +>> + uart3_pins_b: uart3@1 { >> + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; >> + allwinner,function = "uart3"; >> + allwinner,drive = <SUN4I_PINCTRL_10_MA>; diff --git a/a/content_digest b/N1/content_digest index 62c5fd5..8bcae61 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,24 @@ "ref\01454348370-3816-1-git-send-email-andre.przywara@arm.com\0" "ref\01454348370-3816-11-git-send-email-andre.przywara@arm.com\0" "ref\020160205085026.GA1139@lukather\0" - "From\0andre.przywara@arm.com (Andre Przywara)\0" - "Subject\0[PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "From\0Andre Przywara <andre.przywara@arm.com>\0" + "Subject\0Re: [PATCH 10/11] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Mon, 8 Feb 2016 09:42:35 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "Cc\0Chen-Yu Tsai <wens@csie.org>" + linux-sunxi@googlegroups.com + Arnd Bergmann <arnd@arndb.de> + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + devicetree@vger.kernel.org + " Grant Likely <grant.likely@linaro.org>\0" "\00:1\0" "b\0" "Hi,\n" @@ -133,28 +147,28 @@ ">> +\t\t#address-cells = <1>;\n" ">> +\t\t#size-cells = <0>;\n" ">> +\n" - ">> +\t\tcpu at 0 {\n" + ">> +\t\tcpu@0 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <0>;\n" ">> +\t\t\tenable-method = \"psci\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 1 {\n" + ">> +\t\tcpu@1 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <1>;\n" ">> +\t\t\tenable-method = \"psci\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 2 {\n" + ">> +\t\tcpu@2 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <2>;\n" ">> +\t\t\tenable-method = \"psci\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu at 3 {\n" + ">> +\t\tcpu@3 {\n" ">> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" ">> +\t\t\tdevice_type = \"cpu\";\n" ">> +\t\t\treg = <3>;\n" @@ -222,7 +236,7 @@ ">> +\t\t\tclock-output-names = \"osc32k\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll1: clk at 01c20000 {\n" + ">> +\t\tpll1: clk@01c20000 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" ">> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -230,7 +244,7 @@ ">> +\t\t\tclock-output-names = \"pll1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpll6: clk at 01c20028 {\n" + ">> +\t\tpll6: clk@01c20028 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" ">> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -262,7 +276,7 @@ ">> +\t\t\tclock-output-names = \"pll8\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tcpu: cpu_clk at 01c20050 {\n" + ">> +\t\tcpu: cpu_clk@01c20050 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" ">> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -271,7 +285,7 @@ ">> +\t\t\tcritical-clocks = <0>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\taxi: axi_clk at 01c20050 {\n" + ">> +\t\taxi: axi_clk@01c20050 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" ">> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -279,7 +293,7 @@ ">> +\t\t\tclock-output-names = \"axi\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb1: ahb1_clk at 01c20054 {\n" + ">> +\t\tahb1: ahb1_clk@01c20054 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" ">> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -287,7 +301,7 @@ ">> +\t\t\tclock-output-names = \"ahb1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tahb2: ahb2_clk at 01c2005c {\n" + ">> +\t\tahb2: ahb2_clk@01c2005c {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" ">> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -295,7 +309,7 @@ ">> +\t\t\tclock-output-names = \"ahb2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb1: apb1_clk at 01c20054 {\n" + ">> +\t\tapb1: apb1_clk@01c20054 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" ">> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -303,7 +317,7 @@ ">> +\t\t\tclock-output-names = \"apb1\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tapb2: apb2_clk at 01c20058 {\n" + ">> +\t\tapb2: apb2_clk@01c20058 {\n" ">> +\t\t\t#clock-cells = <0>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" ">> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -311,7 +325,7 @@ ">> +\t\t\tclock-output-names = \"apb2\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tbus_gates: clk at 01c20060 {\n" + ">> +\t\tbus_gates: clk@01c20060 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,a64-bus-gates-clk\",\n" ">> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -468,7 +482,7 @@ "I would appreciate if other people could comment on this.\n" "\n" "> \n" - ">> +\t\tmmc0_clk: clk at 01c20088 {\n" + ">> +\t\tmmc0_clk: clk@01c20088 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -478,7 +492,7 @@ ">> +\t\t\t\t\t \"mmc0_sample\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc1_clk: clk at 01c2008c {\n" + ">> +\t\tmmc1_clk: clk@01c2008c {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -488,7 +502,7 @@ ">> +\t\t\t\t\t \"mmc1_sample\";\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc2_clk: clk at 01c20090 {\n" + ">> +\t\tmmc2_clk: clk@01c20090 {\n" ">> +\t\t\t#clock-cells = <1>;\n" ">> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" ">> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -514,7 +528,7 @@ ">> +\t\t#size-cells = <1>;\n" ">> +\t\tranges;\n" ">> +\n" - ">> +\t\tmmc0: mmc at 01c0f000 {\n" + ">> +\t\tmmc0: mmc@01c0f000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c0f000 0x1000>;\n" ">> +\t\t\tclocks = <&bus_gates 8>,\n" @@ -533,7 +547,7 @@ ">> +\t\t\t#size-cells = <0>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc1: mmc at 01c10000 {\n" + ">> +\t\tmmc1: mmc@01c10000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c10000 0x1000>;\n" ">> +\t\t\tclocks = <&bus_gates 9>,\n" @@ -552,7 +566,7 @@ ">> +\t\t\t#size-cells = <0>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tmmc2: mmc at 01c11000 {\n" + ">> +\t\tmmc2: mmc@01c11000 {\n" ">> +\t\t\tcompatible = \"allwinner,sun5i-a13-mmc\";\n" ">> +\t\t\treg = <0x01c11000 0x1000>;\n" ">> +\t\t\tclocks = <&bus_gates 10>,\n" @@ -571,7 +585,7 @@ ">> +\t\t\t#size-cells = <0>;\n" ">> +\t\t};\n" ">> +\n" - ">> +\t\tpio: pinctrl at 01c20800 {\n" + ">> +\t\tpio: pinctrl@01c20800 {\n" ">> +\t\t\tcompatible = \"allwinner,a64-pinctrl\";\n" ">> +\t\t\treg = <0x01c20800 0x400>;\n" ">> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -583,42 +597,42 @@ ">> +\t\t\tinterrupt-controller;\n" ">> +\t\t\t#interrupt-cells = <2>;\n" ">> +\n" - ">> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + ">> +\t\t\tuart0_pins_a: uart0@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" ">> +\t\t\t\tallwinner,function = \"uart0\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + ">> +\t\t\tuart0_pins_b: uart0@1 {\n" ">> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" ">> +\t\t\t\tallwinner,function = \"uart0\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tuart1_pins: uart1 at 0 {\n" + ">> +\t\t\tuart1_pins: uart1@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" ">> +\t\t\t\tallwinner,function = \"uart1\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tuart2_pins: uart2 at 0 {\n" + ">> +\t\t\tuart2_pins: uart2@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" ">> +\t\t\t\tallwinner,function = \"uart2\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + ">> +\t\t\tuart3_pins_a: uart3@0 {\n" ">> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" ">> +\t\t\t\tallwinner,function = \"uart3\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" ">> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" ">> +\t\t\t};\n" ">> +\n" - ">> +\t\t\tuart3_pins_b: uart3 at 1 {\n" + ">> +\t\t\tuart3_pins_b: uart3@1 {\n" ">> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" ">> +\t\t\t\tallwinner,function = \"uart3\";\n" ">> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -639,4 +653,4 @@ "Cheers,\n" Andre -0c2e9a60b91ae3adb7d076c85de878aa7ba804361cba0f484ab34e38880074fa +1966adcc24faaacdc739055a2572d0d1af2d210870ed3e600a77ed7db9a9edd6
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.