diff for duplicates of <56B8B45D.1020902@arm.com> diff --git a/a/1.txt b/N1/1.txt index 8687a08..47e2e5e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -148,28 +148,28 @@ On 08/02/16 09:11, Antoine Tenart wrote: > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a57", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0 0x3>; @@ -208,7 +208,7 @@ On 08/02/16 09:11, Antoine Tenart wrote: This is not a valid interrupt specifier for GICv3, as the 3rd field shouldn't bear this 0xff thing. -> + gic: gic at f0100000 { +> + gic: gic@f0100000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0xf0200000 0x0 0x10000>, /* GIC Dist */ > + <0x0 0xf0280000 0x0 0x200000>, /* GICR */ diff --git a/a/content_digest b/N1/content_digest index b891166..94fe008 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,18 @@ "ref\01454922699-16785-1-git-send-email-antoine.tenart@free-electrons.com\0" "ref\01454922699-16785-3-git-send-email-antoine.tenart@free-electrons.com\0" - "From\0marc.zyngier@arm.com (Marc Zyngier)\0" - "Subject\0[PATCH 2/3] arm64: dts: add the Alpine v2 EVP\0" + "From\0Marc Zyngier <marc.zyngier@arm.com>\0" + "Subject\0Re: [PATCH 2/3] arm64: dts: add the Alpine v2 EVP\0" "Date\0Mon, 8 Feb 2016 15:29:33 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Antoine Tenart <antoine.tenart@free-electrons.com>" + catalin.marinas@arm.com + will.deacon@arm.com + " tsahee@annapurnalabs.com\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + rshitrit@annapurnalabs.com + thomas.petazzoni@free-electrons.com + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + " Barak Wasserstrom <barak@annapurnalabs.com>\0" "\00:1\0" "b\0" "On 08/02/16 09:11, Antoine Tenart wrote:\n" @@ -156,28 +165,28 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a57\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a57\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a57\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a57\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -216,7 +225,7 @@ "This is not a valid interrupt specifier for GICv3, as the 3rd field\n" "shouldn't bear this 0xff thing.\n" "\n" - "> +\t\tgic: gic at f0100000 {\n" + "> +\t\tgic: gic@f0100000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3\";\n" "> +\t\t\treg = <0x0 0xf0200000 0x0 0x10000>,\t/* GIC Dist */\n" "> +\t\t\t <0x0 0xf0280000 0x0 0x200000>,\t/* GICR */\n" @@ -239,4 +248,4 @@ "-- \n" Jazz is not dead. It just smells funny... -7d23f7ffb1df11eae54c096c6500a1c10f5f1de934b315421176986998773b8f +10d2837394df355186a2069b09fcba1e1632ce339960efe4e7051843acc79d76
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