From: Paolo Bonzini <pbonzini@redhat.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>,
joro@8bytes.org, alex.williamson@redhat.com, gleb@kernel.org
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
wei@redhat.com, sherry.hurwitz@amd.com
Subject: Re: [PART1 RFC 5/9] svm: Add VMEXIT handlers for AVIC
Date: Fri, 12 Feb 2016 16:38:26 +0100 [thread overview]
Message-ID: <56BDFC72.7030905@redhat.com> (raw)
In-Reply-To: <1455285574-27892-6-git-send-email-suravee.suthikulpanit@amd.com>
On 12/02/2016 14:59, Suravee Suthikulpanit wrote:
> + "icrh:icrl=%#010x:%08x, id=%u, index=%u\n",
> + __func__, svm->vcpu.cpu, svm->vcpu.vcpu_id,
> + icrh, icrl, id, index);
> +
> + switch (id) {
> + case AVIC_INCMP_IPI_ERR_INVALID_INT_TYPE:
> + /*
> + * AVIC hardware handles the generation of
> + * IPIs when the specified Message Type is Fixed
> + * (also known as fixed delivery mode) and
> + * the Trigger Mode is edge-triggered. The hardware
> + * also supports self and broadcast delivery modes
> + * specified via the Destination Shorthand(DSH)
> + * field of the ICRL. Logical and physical APIC ID
> + * formats are supported. All other IPI types cause
> + * a #VMEXIT, which needs to emulated.
> + */
> + kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
> + kvm_lapic_reg_write(apic, APIC_ICR, icrl);
> + break;
> + case AVIC_INCMP_IPI_ERR_TARGET_NOT_RUN:
> + kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
> + kvm_lapic_reg_write(apic, APIC_ICR, icrl);
Wouldn't this cause a double injection of the IPI if the following happens:
1) destination 1 is running, so the processor sets IRR and sends a
doorbell message
2) destination 2 is not running, so the processor sets IRR and exits
3) destination 1 processes the interrupt, moving it from IRR to ISR
4) destination 1 sends an EOI
5) the source exits and reinjects the interrupt
6) destination 1 then receives the interrupt again.
Or alternatively:
1) destination 1 is not running, so the processor sets IRR and exits
2) another CPU executes VMRUN for destination 1, so the processor
injects the interrupt
3) destination 1 sends an EOI
4) the source exits and reinjects the interrupt
5) destination 1 then receives the interrupt again.
The handling of races for IsRunning and incomplete IPIs has always been
very confusing to me whenever I read the AVIC specification. It would
be great if you could clarify this.
Paolo
> + break;
> + case AVIC_INCMP_IPI_ERR_INV_TARGET:
> + pr_err("SVM: %s: Invalid IPI target (icr=%#08x:%08x, idx=%u)\n",
> + __func__, icrh, icrl, index);
> + BUG();
> + break;
> + case AVIC_INCMP_IPI_ERR_INV_BK_PAGE:
> + pr_err("SVM: %s: Invalid bk page (icr=%#08x:%08x, idx=%u)\n",
> + __func__, icrh, icrl, index);
> + BUG();
next prev parent reply other threads:[~2016-02-12 15:38 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-12 13:59 [PART1 RFC 0/9] KVM: x86: Introduce SVM AVIC support Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 1/9] KVM: x86: Misc LAPIC changes to exposes helper functions Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 2/9] svm: Introduce new AVIC VMCB registers Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 3/9] svm: clean up V_TPR, V_IRQ, V_INTR_PRIO, and V_INTR_MASKING Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 4/9] KVM: x86: Detect and Initialize AVIC support Suravee Suthikulpanit
2016-02-12 14:13 ` Borislav Petkov
2016-02-12 15:46 ` Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 5/9] svm: Add VMEXIT handlers for AVIC Suravee Suthikulpanit
2016-02-12 15:38 ` Paolo Bonzini [this message]
2016-02-15 19:22 ` Radim Krčmář
2016-02-16 6:29 ` Suravee Suthikulpanit
2016-02-16 12:15 ` Paolo Bonzini
2016-02-16 14:13 ` Radim Krčmář
2016-02-16 16:56 ` Paolo Bonzini
2016-02-16 18:06 ` Radim Krčmář
2016-02-16 18:06 ` Radim Krčmář
2016-02-18 2:25 ` Suravee Suthikulpanit
2016-02-18 14:18 ` Radim Krčmář
2016-02-18 14:51 ` Paolo Bonzini
2016-02-18 15:43 ` Radim Krčmář
2016-02-18 15:53 ` Paolo Bonzini
2016-02-18 16:27 ` Radim Krčmář
2016-02-18 17:18 ` Paolo Bonzini
2016-02-19 11:39 ` Suravee Suthikulpanit
2016-02-19 11:44 ` Paolo Bonzini
2016-02-19 11:59 ` Suravee Suthikulpanit
2016-03-03 10:42 ` Suravee Suthikulpanit
2016-03-03 10:50 ` Paolo Bonzini
2016-02-19 11:32 ` Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 6/9] svm: Add interrupt injection via AVIC Suravee Suthikulpanit
2016-02-12 14:16 ` Borislav Petkov
2016-02-12 15:54 ` Suravee Suthikulpanit
2016-02-12 17:14 ` Borislav Petkov
2016-02-12 18:21 ` Paolo Bonzini
2016-02-12 18:30 ` Borislav Petkov
2016-02-12 18:56 ` Paolo Bonzini
2016-02-12 19:33 ` Borislav Petkov
2016-02-16 7:50 ` Ingo Molnar
2016-02-16 8:39 ` [PATCH] x86/msr: Document msr-index.h rule for addition Borislav Petkov
2016-02-12 15:55 ` [PART1 RFC 6/9] svm: Add interrupt injection via AVIC Paolo Bonzini
2016-02-12 16:21 ` Suravee Suthikulpanit
2016-02-12 18:19 ` Paolo Bonzini
2016-02-12 19:36 ` Suravee Suthikulpanit
2016-02-19 11:57 ` Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 7/9] svm: Do not expose x2APIC when enable AVIC Suravee Suthikulpanit
2016-02-12 13:59 ` [PART1 RFC 8/9] svm: Do not intercept CR8 " Suravee Suthikulpanit
2016-02-12 15:48 ` Paolo Bonzini
2016-02-12 13:59 ` [PART1 RFC 9/9] svm: Manage vcpu load/unload " Suravee Suthikulpanit
2016-02-12 15:46 ` Paolo Bonzini
2016-02-12 18:13 ` [PART1 RFC 0/9] KVM: x86: Introduce SVM AVIC support Paolo Bonzini
2016-02-12 19:55 ` Suravee Suthikulpanit
2016-02-12 20:05 ` Paolo Bonzini
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