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Message-ID: <56C084C4.8000509@denx.de>
Date:   Sun, 14 Feb 2016 14:44:36 +0100
From:   Marek Vasut <marex@denx.de>
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To:     Antony Pavlov <antonynpavlov@gmail.com>, linux-mips@linux-mips.org
CC:     Ralf Baechle <ralf@linux-mips.org>, Alban Bedel <albeu@free.fr>,
        Wills Wang <wills.wang@live.com>,
        Daniel Schwierzeck <daniel.schwierzeck@gmail.com>,
        Weijie Gao <hackpascal@gmail.com>
Subject: Re: [PATCH 03/10] MIPS: ath79: Fix the ar724x clock calculation
References: <1455400697-29898-1-git-send-email-antonynpavlov@gmail.com> <1455400697-29898-4-git-send-email-antonynpavlov@gmail.com>
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On 02/13/2016 10:58 PM, Antony Pavlov wrote:
> From: Weijie Gao <hackpascal@gmail.com>
> 
> According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz
> input clock as the REF_CLK instead of 5MHz.

Can't the AR71xx also use 25MHz clock source ?

> The correct CPU PLL calculation procedure is as follows:
> CPU_PLL = (FB * REF_CLK) / REF_DIV / 2.

[...]