Re: [PATCH] MIPS: Octeon: do not change affinity for disabled irqs

[David Daney <ddaney.cavm@gmail.com>]

On 02/15/2016 07:45 AM, Ioan Nicu wrote:
> Octeon sets the default irq affinity to value 1 in the early arch init
> code, so by default all irqs get registered with their affinity set to
> core 0.
>
> When setting one CPU ofline, octeon_irq_cpu_offline_ciu() calls
> irq_set_affinity_locked(), but this function sets the IRQD_AFFINITY_SET bit
> in the irq descriptor. This has the side effect that if one irq is
> requested later, after putting one CPU offline, the affinity of this irq
> would not be the default anymore, but rather forced to "all cores - the
> offline core".
>
> This patch sets the IRQCHIP_ONOFFLINE_ENABLED flag in octeon irq
> controllers, so that the kernel would call the irq_cpu_[on|off]line()
> callbacks only for enabled irqs. If some other irq is requested after
> setting one cpu offline, it would use the default irq affinity, same as it
> would do in the normal case where there is no CPU hotplug operation.
>
> Signed-off-by: Ioan Nicu <ioan.nicu.ext@nokia.com>
> Acked-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>

In principle, I don't object.

I would like to see what tglx has to say about this though.  If we are 
worried about the IRQD_AFFINITY_SET bit, I am not convinced that this is 
the best place to be tweaking code.  Are we papering over something that 
should be handled in a more general manner?  I don't know.

David Daney



> ---
>   arch/mips/cavium-octeon/octeon-irq.c |   15 ++++++++++++---
>   1 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
> index 368eb49..684582e 100644
> --- a/arch/mips/cavium-octeon/octeon-irq.c
> +++ b/arch/mips/cavium-octeon/octeon-irq.c
> @@ -935,6 +935,7 @@ static struct irq_chip octeon_irq_chip_ciu_v2 = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -948,6 +949,7 @@ static struct irq_chip octeon_irq_chip_ciu_v2_edge = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -963,6 +965,7 @@ static struct irq_chip octeon_irq_chip_ciu_sum2 = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -976,6 +979,7 @@ static struct irq_chip octeon_irq_chip_ciu_sum2_edge = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity_sum2,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -988,6 +992,7 @@ static struct irq_chip octeon_irq_chip_ciu = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -1001,6 +1006,7 @@ static struct irq_chip octeon_irq_chip_ciu_edge = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -1041,7 +1047,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
>   #endif
> -	.flags = IRQCHIP_SET_TYPE_MASKED,
> +	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_ONOFFLINE_ENABLED,
>   };
>
>   static struct irq_chip octeon_irq_chip_ciu_gpio = {
> @@ -1056,7 +1062,7 @@ static struct irq_chip octeon_irq_chip_ciu_gpio = {
>   	.irq_set_affinity = octeon_irq_ciu_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
>   #endif
> -	.flags = IRQCHIP_SET_TYPE_MASKED,
> +	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_ONOFFLINE_ENABLED,
>   };
>
>   /*
> @@ -1838,6 +1844,7 @@ static struct irq_chip octeon_irq_chip_ciu2 = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu2_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -1851,6 +1858,7 @@ static struct irq_chip octeon_irq_chip_ciu2_edge = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu2_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
> @@ -1886,7 +1894,7 @@ static struct irq_chip octeon_irq_chip_ciu2_gpio = {
>   	.irq_set_affinity = octeon_irq_ciu2_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
>   #endif
> -	.flags = IRQCHIP_SET_TYPE_MASKED,
> +	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_ONOFFLINE_ENABLED,
>   };
>
>   static int octeon_irq_ciu2_xlat(struct irq_domain *d,
> @@ -2537,6 +2545,7 @@ static struct irq_chip octeon_irq_chip_ciu3 = {
>   #ifdef CONFIG_SMP
>   	.irq_set_affinity = octeon_irq_ciu3_set_affinity,
>   	.irq_cpu_offline = octeon_irq_cpu_offline_ciu,
> +	.flags = IRQCHIP_ONOFFLINE_ENABLED,
>   #endif
>   };
>
>