diff for duplicates of <56C48FF7.90904@arm.com> diff --git a/a/1.txt b/N1/1.txt index 8692cd7..d8f8a9e 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -28,7 +28,7 @@ Changelog v1..v2: Cheers, Andre. -> Signed-off-by: Andre Przywara <andre.przywara@arm.com> +> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> > --- > Documentation/devicetree/bindings/arm/sunxi.txt | 1 + > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + @@ -66,7 +66,7 @@ Andre. > +/* > + * Copyright (C) 2016 ARM Ltd. > + * based on the Allwinner H3 dtsi: -> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> +> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -119,28 +119,28 @@ Andre. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; @@ -158,7 +158,7 @@ Andre. > + reg = <0x40000000 0>; > + }; > + -> + gic: interrupt-controller at 01c81000 { +> + gic: interrupt-controller@01c81000 { > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -203,7 +203,7 @@ Andre. > + clock-output-names = "osc32k"; > + }; > + -> + pll1: pll1_clk at 01c20000 { +> + pll1: pll1_clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -211,7 +211,7 @@ Andre. > + clock-output-names = "pll1"; > + }; > + -> + pll6: pll6_clk at 01c20028 { +> + pll6: pll6_clk@01c20028 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -237,7 +237,7 @@ Andre. > + clock-output-names = "pll6d2"; > + }; > + -> + pll8: pll8_clk at 01c2002c { +> + pll8: pll8_clk@01c2002c { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c2002c 0x4>; @@ -254,7 +254,7 @@ Andre. > + clock-output-names = "pll8x2"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -263,7 +263,7 @@ Andre. > + critical-clocks = <0>; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -271,7 +271,7 @@ Andre. > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -279,7 +279,7 @@ Andre. > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -287,7 +287,7 @@ Andre. > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -295,7 +295,7 @@ Andre. > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -303,7 +303,7 @@ Andre. > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: bus_gates_clk at 01c20060 { +> + bus_gates: bus_gates_clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun50i-a64-bus-gates-clk", > + "allwinner,sunxi-multi-bus-gates-clk"; @@ -370,7 +370,7 @@ Andre. > + }; > + }; > + -> + mmc0_clk: mmc0_clk at 01c20088 { +> + mmc0_clk: mmc0_clk@01c20088 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20088 0x4>; @@ -378,7 +378,7 @@ Andre. > + clock-output-names = "mmc0"; > + }; > + -> + mmc1_clk: mmc1_clk at 01c2008c { +> + mmc1_clk: mmc1_clk@01c2008c { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c2008c 0x4>; @@ -386,7 +386,7 @@ Andre. > + clock-output-names = "mmc1"; > + }; > + -> + mmc2_clk: mmc2_clk at 01c20090 { +> + mmc2_clk: mmc2_clk@01c20090 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20090 0x4>; @@ -401,7 +401,7 @@ Andre. > + #size-cells = <1>; > + ranges; > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; @@ -417,7 +417,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; @@ -433,7 +433,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; @@ -449,7 +449,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun50i-a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -461,84 +461,84 @@ Andre. > + interrupt-controller; > + #interrupt-cells = <2>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0 at 1 { +> + uart0_pins_b: uart0@1 { > + allwinner,pins = "PF2", "PF3"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_2pins: uart1_2 at 0 { +> + uart1_2pins: uart1_2@0 { > + allwinner,pins = "PG6", "PG7"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_4pins: uart1_4 at 0 { +> + uart1_4pins: uart1_4@0 { > + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_2pins: uart2_2 at 0 { +> + uart2_2pins: uart2_2@0 { > + allwinner,pins = "PB0", "PB1"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_4pins: uart2_4 at 0 { +> + uart2_4pins: uart2_4@0 { > + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_a: uart3 at 0 { +> + uart3_pins_a: uart3@0 { > + allwinner,pins = "PD0", "PD1"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_2pins_b: uart3_2 at 1 { +> + uart3_2pins_b: uart3_2@1 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_4pins_b: uart3_4 at 1 { +> + uart3_4pins_b: uart3_4@1 { > + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart4_2pins: uart4_2 at 0 { +> + uart4_2pins: uart4_2@0 { > + allwinner,pins = "PD2", "PD3"; > + allwinner,function = "uart4"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart4_4pins: uart4_4 at 0 { +> + uart4_4pins: uart4_4@0 { > + allwinner,pins = "PD2", "PD3", "PD4", "PD5"; > + allwinner,function = "uart4"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_pins: mmc0 at 0 { +> + mmc0_pins: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", "PF3", > + "PF4", "PF5"; > + allwinner,function = "mmc0"; @@ -546,14 +546,14 @@ Andre. > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_default_cd_pin: mmc0_cd_pin at 0 { +> + mmc0_default_cd_pin: mmc0_cd_pin@0 { > + allwinner,pins = "PF6"; > + allwinner,function = "gpio_in"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; > + }; > + -> + mmc1_pins: mmc1 at 0 { +> + mmc1_pins: mmc1@0 { > + allwinner,pins = "PG0", "PG1", "PG2", "PG3", > + "PG4", "PG5"; > + allwinner,function = "mmc1"; @@ -561,7 +561,7 @@ Andre. > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc2_pins: mmc2 at 0 { +> + mmc2_pins: mmc2@0 { > + allwinner,pins = "PC1", "PC5", "PC6", "PC8", > + "PC9", "PC10"; > + allwinner,function = "mmc2"; @@ -591,25 +591,25 @@ Andre. > + }; > + }; > + -> + ahb_rst: reset at 01c202c0 { +> + ahb_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202c0 0xc>; > + }; > + -> + apb1_rst: reset at 01c202d0 { +> + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + -> + apb2_rst: reset at 01c202d8 { +> + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -620,7 +620,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart1: serial at 01c28400 { +> + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -631,7 +631,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart2: serial at 01c28800 { +> + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -642,7 +642,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart3: serial at 01c28c00 { +> + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -653,7 +653,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart4: serial at 01c29000 { +> + uart4: serial@01c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -664,14 +664,14 @@ Andre. > + status = "disabled"; > + }; > + -> + rtc: rtc at 01f00000 { +> + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + i2c0: i2c at 01c2ac00 { +> + i2c0: i2c@01c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -682,7 +682,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + i2c1: i2c at 01c2b000 { +> + i2c1: i2c@01c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -693,7 +693,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + i2c2: i2c at 01c2b400 { +> + i2c2: i2c@01c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; @@ -705,4 +705,8 @@ Andre. > + }; > + }; > +}; -> +> +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index a2ced94..9c0807d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,23 @@ "ref\01455709440-8668-1-git-send-email-andre.przywara@arm.com\0" "ref\01455709440-8668-6-git-send-email-andre.przywara@arm.com\0" - "From\0andre.przywara@arm.com (Andre Przywara)\0" - "Subject\0[PATCH v2 5/8] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "ref\01455709440-8668-6-git-send-email-andre.przywara-5wv7dgnIgG8@public.gmane.org\0" + "From\0Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH v2 5/8] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Wed, 17 Feb 2016 15:21:27 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>" + Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> + " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org\0" + "Cc\0Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>" + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org> + Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> + Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> + Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "Just saw that I forgot the Changelog, sorry about that.\n" @@ -36,7 +50,7 @@ "Cheers,\n" "Andre.\n" "\n" - "> Signed-off-by: Andre Przywara <andre.przywara@arm.com>\n" + "> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>\n" "> ---\n" "> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +\n" "> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +\n" @@ -74,7 +88,7 @@ "> +/*\n" "> + * Copyright (C) 2016 ARM Ltd.\n" "> + * based on the Allwinner H3 dtsi:\n" - "> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>\n" + "> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -127,28 +141,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -166,7 +180,7 @@ "> +\t\treg = <0x40000000 0>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 01c81000 {\n" + "> +\tgic: interrupt-controller@01c81000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\tinterrupt-controller;\n" "> +\t\t#interrupt-cells = <3>;\n" @@ -211,7 +225,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: pll1_clk at 01c20000 {\n" + "> +\t\tpll1: pll1_clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -219,7 +233,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: pll6_clk at 01c20028 {\n" + "> +\t\tpll6: pll6_clk@01c20028 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -245,7 +259,7 @@ "> +\t\t\tclock-output-names = \"pll6d2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll8: pll8_clk at 01c2002c {\n" + "> +\t\tpll8: pll8_clk@01c2002c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c2002c 0x4>;\n" @@ -262,7 +276,7 @@ "> +\t\t\tclock-output-names = \"pll8x2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -271,7 +285,7 @@ "> +\t\t\tcritical-clocks = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -279,7 +293,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -287,7 +301,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -295,7 +309,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -303,7 +317,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -311,7 +325,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: bus_gates_clk at 01c20060 {\n" + "> +\t\tbus_gates: bus_gates_clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-bus-gates-clk\",\n" "> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -378,7 +392,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: mmc0_clk at 01c20088 {\n" + "> +\t\tmmc0_clk: mmc0_clk@01c20088 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -386,7 +400,7 @@ "> +\t\t\tclock-output-names = \"mmc0\";\n" "> + };\n" "> +\n" - "> +\t\tmmc1_clk: mmc1_clk at 01c2008c {\n" + "> +\t\tmmc1_clk: mmc1_clk@01c2008c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -394,7 +408,7 @@ "> +\t\t\tclock-output-names = \"mmc1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: mmc2_clk at 01c20090 {\n" + "> +\t\tmmc2_clk: mmc2_clk@01c20090 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -409,7 +423,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\",\n" "> +\t\t\t\t \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" @@ -425,7 +439,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\",\n" "> +\t\t\t\t \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" @@ -441,7 +455,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\",\n" "> +\t\t\t\t \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" @@ -457,7 +471,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-pinctrl\";\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -469,84 +483,84 @@ "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <2>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> +\t\t\tuart0_pins_b: uart0@1 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_2pins: uart1_2 at 0 {\n" + "> +\t\t\tuart1_2pins: uart1_2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_4pins: uart1_4 at 0 {\n" + "> +\t\t\tuart1_4pins: uart1_4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_2pins: uart2_2 at 0 {\n" + "> +\t\t\tuart2_2pins: uart2_2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_4pins: uart2_4 at 0 {\n" + "> +\t\t\tuart2_4pins: uart2_4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> +\t\t\tuart3_pins_a: uart3@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_2pins_b: uart3_2 at 1 {\n" + "> +\t\t\tuart3_2pins_b: uart3_2@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_4pins_b: uart3_4 at 1 {\n" + "> +\t\t\tuart3_4pins_b: uart3_4@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4_2pins: uart4_2 at 0 {\n" + "> +\t\t\tuart4_2pins: uart4_2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD2\", \"PD3\";\n" "> +\t\t\t\tallwinner,function = \"uart4\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4_4pins: uart4_4 at 0 {\n" + "> +\t\t\tuart4_4pins: uart4_4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD2\", \"PD3\", \"PD4\", \"PD5\";\n" "> +\t\t\t\tallwinner,function = \"uart4\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_pins: mmc0 at 0 {\n" + "> +\t\t\tmmc0_pins: mmc0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n" "> +\t\t\t\t\t\t \"PF4\", \"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" @@ -554,14 +568,14 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin at 0 {\n" + "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF6\";\n" "> +\t\t\t\tallwinner,function = \"gpio_in\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins: mmc1 at 0 {\n" + "> +\t\t\tmmc1_pins: mmc1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n" "> +\t\t\t\t\t\t \"PG4\", \"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" @@ -569,7 +583,7 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc2_pins: mmc2 at 0 {\n" + "> +\t\t\tmmc2_pins: mmc2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PC1\", \"PC5\", \"PC6\", \"PC8\",\n" "> +\t\t\t\t\t\t \"PC9\", \"PC10\";\n" "> +\t\t\t\tallwinner,function = \"mmc2\";\n" @@ -599,25 +613,25 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb_rst: reset at 01c202c0 {\n" + "> +\t\tahb_rst: reset@01c202c0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202c0 0xc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_rst: reset at 01c202d0 {\n" + "> +\t\tapb1_rst: reset@01c202d0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d0 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_rst: reset at 01c202d8 {\n" + "> +\t\tapb2_rst: reset@01c202d8 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d8 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -628,7 +642,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial at 01c28400 {\n" + "> +\t\tuart1: serial@01c28400 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -639,7 +653,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 01c28800 {\n" + "> +\t\tuart2: serial@01c28800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -650,7 +664,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial at 01c28c00 {\n" + "> +\t\tuart3: serial@01c28c00 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -661,7 +675,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart4: serial at 01c29000 {\n" + "> +\t\tuart4: serial@01c29000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c29000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -672,14 +686,14 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\trtc: rtc at 01f00000 {\n" + "> +\t\trtc: rtc@01f00000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> +\t\t\treg = <0x01f00000 0x54>;\n" "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at 01c2ac00 {\n" + "> +\t\ti2c0: i2c@01c2ac00 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2ac00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -690,7 +704,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at 01c2b000 {\n" + "> +\t\ti2c1: i2c@01c2b000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -701,7 +715,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at 01c2b400 {\n" + "> +\t\ti2c2: i2c@01c2b400 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -713,6 +727,10 @@ "> +\t\t};\n" "> +\t};\n" "> +};\n" - > + "> \n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -9725995074d6c49365b6e6252b8069154afd3678e389a8a784f87b91fad120d9 +8c1afe744faf880c7cd95fd51e208621446682e4b0f9fe43ab5bae39bf3fedaf
diff --git a/a/1.txt b/N2/1.txt index 8692cd7..0db657f 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -119,28 +119,28 @@ Andre. > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0>; > + enable-method = "psci"; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <1>; > + enable-method = "psci"; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <2>; > + enable-method = "psci"; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <3>; @@ -158,7 +158,7 @@ Andre. > + reg = <0x40000000 0>; > + }; > + -> + gic: interrupt-controller at 01c81000 { +> + gic: interrupt-controller@01c81000 { > + compatible = "arm,gic-400"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -203,7 +203,7 @@ Andre. > + clock-output-names = "osc32k"; > + }; > + -> + pll1: pll1_clk at 01c20000 { +> + pll1: pll1_clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -211,7 +211,7 @@ Andre. > + clock-output-names = "pll1"; > + }; > + -> + pll6: pll6_clk at 01c20028 { +> + pll6: pll6_clk@01c20028 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -237,7 +237,7 @@ Andre. > + clock-output-names = "pll6d2"; > + }; > + -> + pll8: pll8_clk at 01c2002c { +> + pll8: pll8_clk@01c2002c { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c2002c 0x4>; @@ -254,7 +254,7 @@ Andre. > + clock-output-names = "pll8x2"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -263,7 +263,7 @@ Andre. > + critical-clocks = <0>; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -271,7 +271,7 @@ Andre. > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -279,7 +279,7 @@ Andre. > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -287,7 +287,7 @@ Andre. > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -295,7 +295,7 @@ Andre. > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -303,7 +303,7 @@ Andre. > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: bus_gates_clk at 01c20060 { +> + bus_gates: bus_gates_clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun50i-a64-bus-gates-clk", > + "allwinner,sunxi-multi-bus-gates-clk"; @@ -370,7 +370,7 @@ Andre. > + }; > + }; > + -> + mmc0_clk: mmc0_clk at 01c20088 { +> + mmc0_clk: mmc0_clk@01c20088 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20088 0x4>; @@ -378,7 +378,7 @@ Andre. > + clock-output-names = "mmc0"; > + }; > + -> + mmc1_clk: mmc1_clk at 01c2008c { +> + mmc1_clk: mmc1_clk@01c2008c { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c2008c 0x4>; @@ -386,7 +386,7 @@ Andre. > + clock-output-names = "mmc1"; > + }; > + -> + mmc2_clk: mmc2_clk at 01c20090 { +> + mmc2_clk: mmc2_clk@01c20090 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-mod0-clk"; > + reg = <0x01c20090 0x4>; @@ -401,7 +401,7 @@ Andre. > + #size-cells = <1>; > + ranges; > + -> + mmc0: mmc at 01c0f000 { +> + mmc0: mmc@01c0f000 { > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; > + reg = <0x01c0f000 0x1000>; @@ -417,7 +417,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + mmc1: mmc at 01c10000 { +> + mmc1: mmc@01c10000 { > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; > + reg = <0x01c10000 0x1000>; @@ -433,7 +433,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + mmc2: mmc at 01c11000 { +> + mmc2: mmc@01c11000 { > + compatible = "allwinner,sun50i-a64-mmc", > + "allwinner,sun5i-a13-mmc"; > + reg = <0x01c11000 0x1000>; @@ -449,7 +449,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + pio: pinctrl at 01c20800 { +> + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun50i-a64-pinctrl"; > + reg = <0x01c20800 0x400>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -461,84 +461,84 @@ Andre. > + interrupt-controller; > + #interrupt-cells = <2>; > + -> + uart0_pins_a: uart0 at 0 { +> + uart0_pins_a: uart0@0 { > + allwinner,pins = "PB8", "PB9"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart0_pins_b: uart0 at 1 { +> + uart0_pins_b: uart0@1 { > + allwinner,pins = "PF2", "PF3"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_2pins: uart1_2 at 0 { +> + uart1_2pins: uart1_2@0 { > + allwinner,pins = "PG6", "PG7"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart1_4pins: uart1_4 at 0 { +> + uart1_4pins: uart1_4@0 { > + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; > + allwinner,function = "uart1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_2pins: uart2_2 at 0 { +> + uart2_2pins: uart2_2@0 { > + allwinner,pins = "PB0", "PB1"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart2_4pins: uart2_4 at 0 { +> + uart2_4pins: uart2_4@0 { > + allwinner,pins = "PB0", "PB1", "PB2", "PB3"; > + allwinner,function = "uart2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_pins_a: uart3 at 0 { +> + uart3_pins_a: uart3@0 { > + allwinner,pins = "PD0", "PD1"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_2pins_b: uart3_2 at 1 { +> + uart3_2pins_b: uart3_2@1 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart3_4pins_b: uart3_4 at 1 { +> + uart3_4pins_b: uart3_4@1 { > + allwinner,pins = "PH4", "PH5", "PH6", "PH7"; > + allwinner,function = "uart3"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart4_2pins: uart4_2 at 0 { +> + uart4_2pins: uart4_2@0 { > + allwinner,pins = "PD2", "PD3"; > + allwinner,function = "uart4"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + uart4_4pins: uart4_4 at 0 { +> + uart4_4pins: uart4_4@0 { > + allwinner,pins = "PD2", "PD3", "PD4", "PD5"; > + allwinner,function = "uart4"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_pins: mmc0 at 0 { +> + mmc0_pins: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", "PF3", > + "PF4", "PF5"; > + allwinner,function = "mmc0"; @@ -546,14 +546,14 @@ Andre. > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_default_cd_pin: mmc0_cd_pin at 0 { +> + mmc0_default_cd_pin: mmc0_cd_pin@0 { > + allwinner,pins = "PF6"; > + allwinner,function = "gpio_in"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; > + }; > + -> + mmc1_pins: mmc1 at 0 { +> + mmc1_pins: mmc1@0 { > + allwinner,pins = "PG0", "PG1", "PG2", "PG3", > + "PG4", "PG5"; > + allwinner,function = "mmc1"; @@ -561,7 +561,7 @@ Andre. > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc2_pins: mmc2 at 0 { +> + mmc2_pins: mmc2@0 { > + allwinner,pins = "PC1", "PC5", "PC6", "PC8", > + "PC9", "PC10"; > + allwinner,function = "mmc2"; @@ -591,25 +591,25 @@ Andre. > + }; > + }; > + -> + ahb_rst: reset at 01c202c0 { +> + ahb_rst: reset@01c202c0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202c0 0xc>; > + }; > + -> + apb1_rst: reset at 01c202d0 { +> + apb1_rst: reset@01c202d0 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d0 0x4>; > + }; > + -> + apb2_rst: reset at 01c202d8 { +> + apb2_rst: reset@01c202d8 { > + #reset-cells = <1>; > + compatible = "allwinner,sun6i-a31-clock-reset"; > + reg = <0x01c202d8 0x4>; > + }; > + -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -620,7 +620,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart1: serial at 01c28400 { +> + uart1: serial@01c28400 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28400 0x400>; > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; @@ -631,7 +631,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart2: serial at 01c28800 { +> + uart2: serial@01c28800 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28800 0x400>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; @@ -642,7 +642,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart3: serial at 01c28c00 { +> + uart3: serial@01c28c00 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28c00 0x400>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; @@ -653,7 +653,7 @@ Andre. > + status = "disabled"; > + }; > + -> + uart4: serial at 01c29000 { +> + uart4: serial@01c29000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c29000 0x400>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; @@ -664,14 +664,14 @@ Andre. > + status = "disabled"; > + }; > + -> + rtc: rtc at 01f00000 { +> + rtc: rtc@01f00000 { > + compatible = "allwinner,sun6i-a31-rtc"; > + reg = <0x01f00000 0x54>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + i2c0: i2c at 01c2ac00 { +> + i2c0: i2c@01c2ac00 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2ac00 0x400>; > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; @@ -682,7 +682,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + i2c1: i2c at 01c2b000 { +> + i2c1: i2c@01c2b000 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b000 0x400>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -693,7 +693,7 @@ Andre. > + #size-cells = <0>; > + }; > + -> + i2c2: i2c at 01c2b400 { +> + i2c2: i2c@01c2b400 { > + compatible = "allwinner,sun6i-a31-i2c"; > + reg = <0x01c2b400 0x400>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N2/content_digest index a2ced94..7559253 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,22 @@ "ref\01455709440-8668-1-git-send-email-andre.przywara@arm.com\0" "ref\01455709440-8668-6-git-send-email-andre.przywara@arm.com\0" - "From\0andre.przywara@arm.com (Andre Przywara)\0" - "Subject\0[PATCH v2 5/8] arm64: dts: add Allwinner A64 SoC .dtsi\0" + "From\0Andre Przywara <andre.przywara@arm.com>\0" + "Subject\0Re: [PATCH v2 5/8] arm64: dts: add Allwinner A64 SoC .dtsi\0" "Date\0Wed, 17 Feb 2016 15:21:27 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Maxime Ripard <maxime.ripard@free-electrons.com>" + Chen-Yu Tsai <wens@csie.org> + " linux-sunxi@googlegroups.com\0" + "Cc\0Arnd Bergmann <arnd@arndb.de>" + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + Catalin Marinas <catalin.marinas@arm.com> + Will Deacon <will.deacon@arm.com> + Rob Herring <robh+dt@kernel.org> + Pawel Moll <pawel.moll@arm.com> + Mark Rutland <mark.rutland@arm.com> + Ian Campbell <ijc+devicetree@hellion.org.uk> + Kumar Gala <galak@codeaurora.org> + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Just saw that I forgot the Changelog, sorry about that.\n" @@ -127,28 +140,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -166,7 +179,7 @@ "> +\t\treg = <0x40000000 0>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 01c81000 {\n" + "> +\tgic: interrupt-controller@01c81000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\tinterrupt-controller;\n" "> +\t\t#interrupt-cells = <3>;\n" @@ -211,7 +224,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: pll1_clk at 01c20000 {\n" + "> +\t\tpll1: pll1_clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -219,7 +232,7 @@ "> +\t\t\tclock-output-names = \"pll1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: pll6_clk at 01c20028 {\n" + "> +\t\tpll6: pll6_clk@01c20028 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -245,7 +258,7 @@ "> +\t\t\tclock-output-names = \"pll6d2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll8: pll8_clk at 01c2002c {\n" + "> +\t\tpll8: pll8_clk@01c2002c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c2002c 0x4>;\n" @@ -262,7 +275,7 @@ "> +\t\t\tclock-output-names = \"pll8x2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -271,7 +284,7 @@ "> +\t\t\tcritical-clocks = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -279,7 +292,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -287,7 +300,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -295,7 +308,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -303,7 +316,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -311,7 +324,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: bus_gates_clk at 01c20060 {\n" + "> +\t\tbus_gates: bus_gates_clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-bus-gates-clk\",\n" "> +\t\t\t\t \"allwinner,sunxi-multi-bus-gates-clk\";\n" @@ -378,7 +391,7 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: mmc0_clk at 01c20088 {\n" + "> +\t\tmmc0_clk: mmc0_clk@01c20088 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -386,7 +399,7 @@ "> +\t\t\tclock-output-names = \"mmc0\";\n" "> + };\n" "> +\n" - "> +\t\tmmc1_clk: mmc1_clk at 01c2008c {\n" + "> +\t\tmmc1_clk: mmc1_clk@01c2008c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -394,7 +407,7 @@ "> +\t\t\tclock-output-names = \"mmc1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: mmc2_clk at 01c20090 {\n" + "> +\t\tmmc2_clk: mmc2_clk@01c20090 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -409,7 +422,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tmmc0: mmc at 01c0f000 {\n" + "> +\t\tmmc0: mmc@01c0f000 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\",\n" "> +\t\t\t\t \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c0f000 0x1000>;\n" @@ -425,7 +438,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1: mmc at 01c10000 {\n" + "> +\t\tmmc1: mmc@01c10000 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\",\n" "> +\t\t\t\t \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c10000 0x1000>;\n" @@ -441,7 +454,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2: mmc at 01c11000 {\n" + "> +\t\tmmc2: mmc@01c11000 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-mmc\",\n" "> +\t\t\t\t \"allwinner,sun5i-a13-mmc\";\n" "> +\t\t\treg = <0x01c11000 0x1000>;\n" @@ -457,7 +470,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tpio: pinctrl at 01c20800 {\n" + "> +\t\tpio: pinctrl@01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,sun50i-a64-pinctrl\";\n" "> +\t\t\treg = <0x01c20800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -469,84 +482,84 @@ "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <2>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" + "> +\t\t\tuart0_pins_a: uart0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB8\", \"PB9\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0_pins_b: uart0 at 1 {\n" + "> +\t\t\tuart0_pins_b: uart0@1 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF3\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_2pins: uart1_2 at 0 {\n" + "> +\t\t\tuart1_2pins: uart1_2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1_4pins: uart1_4 at 0 {\n" + "> +\t\t\tuart1_4pins: uart1_4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG6\", \"PG7\", \"PG8\", \"PG9\";\n" "> +\t\t\t\tallwinner,function = \"uart1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_2pins: uart2_2 at 0 {\n" + "> +\t\t\tuart2_2pins: uart2_2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart2_4pins: uart2_4 at 0 {\n" + "> +\t\t\tuart2_4pins: uart2_4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PB0\", \"PB1\", \"PB2\", \"PB3\";\n" "> +\t\t\t\tallwinner,function = \"uart2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_pins_a: uart3 at 0 {\n" + "> +\t\t\tuart3_pins_a: uart3@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD0\", \"PD1\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_2pins_b: uart3_2 at 1 {\n" + "> +\t\t\tuart3_2pins_b: uart3_2@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart3_4pins_b: uart3_4 at 1 {\n" + "> +\t\t\tuart3_4pins_b: uart3_4@1 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\", \"PH6\", \"PH7\";\n" "> +\t\t\t\tallwinner,function = \"uart3\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4_2pins: uart4_2 at 0 {\n" + "> +\t\t\tuart4_2pins: uart4_2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD2\", \"PD3\";\n" "> +\t\t\t\tallwinner,function = \"uart4\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart4_4pins: uart4_4 at 0 {\n" + "> +\t\t\tuart4_4pins: uart4_4@0 {\n" "> +\t\t\t\tallwinner,pins = \"PD2\", \"PD3\", \"PD4\", \"PD5\";\n" "> +\t\t\t\tallwinner,function = \"uart4\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_pins: mmc0 at 0 {\n" + "> +\t\t\tmmc0_pins: mmc0@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\", \"PF3\",\n" "> +\t\t\t\t\t\t \"PF4\", \"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" @@ -554,14 +567,14 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin at 0 {\n" + "> +\t\t\tmmc0_default_cd_pin: mmc0_cd_pin@0 {\n" "> +\t\t\t\tallwinner,pins = \"PF6\";\n" "> +\t\t\t\tallwinner,function = \"gpio_in\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins: mmc1 at 0 {\n" + "> +\t\t\tmmc1_pins: mmc1@0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\", \"PG1\", \"PG2\", \"PG3\",\n" "> +\t\t\t\t\t\t \"PG4\", \"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" @@ -569,7 +582,7 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc2_pins: mmc2 at 0 {\n" + "> +\t\t\tmmc2_pins: mmc2@0 {\n" "> +\t\t\t\tallwinner,pins = \"PC1\", \"PC5\", \"PC6\", \"PC8\",\n" "> +\t\t\t\t\t\t \"PC9\", \"PC10\";\n" "> +\t\t\t\tallwinner,function = \"mmc2\";\n" @@ -599,25 +612,25 @@ "> +\t\t\t};\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb_rst: reset at 01c202c0 {\n" + "> +\t\tahb_rst: reset@01c202c0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202c0 0xc>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1_rst: reset at 01c202d0 {\n" + "> +\t\tapb1_rst: reset@01c202d0 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d0 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2_rst: reset at 01c202d8 {\n" + "> +\t\tapb2_rst: reset@01c202d8 {\n" "> +\t\t\t#reset-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n" "> +\t\t\treg = <0x01c202d8 0x4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -628,7 +641,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart1: serial at 01c28400 {\n" + "> +\t\tuart1: serial@01c28400 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -639,7 +652,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart2: serial at 01c28800 {\n" + "> +\t\tuart2: serial@01c28800 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28800 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -650,7 +663,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart3: serial at 01c28c00 {\n" + "> +\t\tuart3: serial@01c28c00 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28c00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -661,7 +674,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart4: serial at 01c29000 {\n" + "> +\t\tuart4: serial@01c29000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c29000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -672,14 +685,14 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\trtc: rtc at 01f00000 {\n" + "> +\t\trtc: rtc@01f00000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-rtc\";\n" "> +\t\t\treg = <0x01f00000 0x54>;\n" "> +\t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t\t <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c0: i2c at 01c2ac00 {\n" + "> +\t\ti2c0: i2c@01c2ac00 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2ac00 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -690,7 +703,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c1: i2c at 01c2b000 {\n" + "> +\t\ti2c1: i2c@01c2b000 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -701,7 +714,7 @@ "> +\t\t\t#size-cells = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ti2c2: i2c at 01c2b400 {\n" + "> +\t\ti2c2: i2c@01c2b400 {\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n" "> +\t\t\treg = <0x01c2b400 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -715,4 +728,4 @@ "> +};\n" > -9725995074d6c49365b6e6252b8069154afd3678e389a8a784f87b91fad120d9 +076eaa6156f5c76a789689c95132ef8d84081a62818f29dad045046ac539d16a
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.