From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38797) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWept-0000g5-5O for qemu-devel@nongnu.org; Fri, 19 Feb 2016 01:46:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWepp-0003CQ-Tl for qemu-devel@nongnu.org; Fri, 19 Feb 2016 01:46:41 -0500 Received: from mout.web.de ([212.227.15.3]:49581) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWepp-0003Bn-Jn for qemu-devel@nongnu.org; Fri, 19 Feb 2016 01:46:37 -0500 References: <1455852618-5224-1-git-send-email-peterx@redhat.com> From: Jan Kiszka Message-ID: <56C6BA42.1050302@web.de> Date: Fri, 19 Feb 2016 07:46:26 +0100 MIME-Version: 1.0 In-Reply-To: <1455852618-5224-1-git-send-email-peterx@redhat.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="567FBSf1mfMn73RwOKhGcAmELArvJQUvi" Subject: Re: [Qemu-devel] [PATCH 00/13] IOMMU: Enable interrupt remapping for Intel IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu , qemu-devel@nongnu.org Cc: Rita Sinha , ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , imammedo@redhat.com, pbonzini@redhat.com, rth@twiddle.net This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --567FBSf1mfMn73RwOKhGcAmELArvJQUvi Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable Hi Peter, On 2016-02-19 04:30, Peter Xu wrote: > This patchset provide very basic functionalities for interrupt > remapping (IR) support of the emulated Intel IOMMU device. Interesting. Some questions: - Were you aware of http://git.kiszka.org/?p=3Dqemu.git;a=3Dshortlog;h=3Drefs/heads/queues/vt= d-intremap, and can you comment on how this relates to your approach? Mine included HPET support, e.g. - Rita Sinha is currently working on integrating my old patches with the split-irqchip to get KVM working (as an Outreachy project). It's probably a bit unfortunate to consider a different horse that late in to project. What do you think, how could we benefit from each other? - Radim was telling me to look on this as well. How do your efforts correlate? >=20 > By default, IR is disabled to be better compatible with current > QEMU. To enable IR, we can using the following command to boot a > IR-supported VM with basic network (still do not support kvm-ioapic, > so we need to specify kernel_irqchip=3Doff here): >=20 > $ qemu-system-x86_64 -M q35,iommu=3Don,int_remap=3Don,kernel_irqchip=3D= off \ > -enable-kvm -m 1024 -s \ > -monitor telnet::3333,server,nowait \ > -netdev user,id=3Duser.0,hostfwd=3Dtcp::5555-:22 \ > -device virtio-net-pci,netdev=3Duser.0 \ > /var/lib/libvirt/images/vm1.qcow2 >=20 > When guest boots, we can verify whether IR enabled by grepping the > dmesg like: >=20 > [root@localhost ~]# journalctl -k | grep "DMAR-IR" > Feb 19 11:21:23 localhost.localdomain kernel: DMAR-IR: IOAPIC id 0 unde= r DRHD base 0xfed90000 IOMMU 0 > Feb 19 11:21:23 localhost.localdomain kernel: DMAR-IR: Enabled IRQ rema= pping in xapic mode >=20 > Currently only two devices are supported: >=20 > - Emulated IOAPIC device > - PCI Devices >=20 > TODO List: >=20 > - kvm-ioapic support > - vhost support > - pass through device support > - EIM support > - IR fault reporting > - source-id validation for IRTE > - IRTE cache and better queued invalidation > - migration support (for IOMMU as general?) > - more? >=20 > Peter Xu (13): > q35: add "int-remap" flag to enable intr > acpi: enable INTR for DMAR report structure > intel_iommu: allow queued invalidation for IR > intel_iommu: set IR bit for ECAP register > acpi: add DMAR scope definition for root IOAPIC > intel_iommu: define interrupt remap table addr register > intel_iommu: handle interrupt remap enable > intel_iommu: define several structs for IOMMU IR > intel_iommu: provide helper function vtd_get_iommu > ioapic-common: add iommu for IOAPICCommonState > intel_iommu: add IR translation faults defines > intel_iommu: ioapic: IR support for emulated IOAPIC > intel_iommu: Add support for PCI MSI remap >=20 > hw/core/machine.c | 20 ++ > hw/i386/acpi-build.c | 41 +++- > hw/i386/intel_iommu.c | 397 ++++++++++++++++++++++++++++++= +++++++- > hw/i386/intel_iommu_internal.h | 25 +++ > hw/intc/ioapic.c | 36 +++- > hw/intc/ioapic_common.c | 2 + > hw/pci-host/q35.c | 6 +- > include/hw/acpi/acpi-defs.h | 15 ++ > include/hw/boards.h | 1 + > include/hw/i386/intel_iommu.h | 121 ++++++++++++ > include/hw/i386/ioapic_internal.h | 3 + > include/hw/pci/msi.h | 4 + > 12 files changed, 651 insertions(+), 20 deletions(-) >=20 Is there a git tree with your patches somewhere? Thanks, Jan --567FBSf1mfMn73RwOKhGcAmELArvJQUvi Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlbGukIACgkQitSsb3rl5xTH0wCgjM3/TJywhqo58TjIB24PjAW/ kH0AoIuNccUobzjLNXDbM7mjV4mYjYJ9 =r5AZ -----END PGP SIGNATURE----- --567FBSf1mfMn73RwOKhGcAmELArvJQUvi--