From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Fri, 19 Feb 2016 14:15:46 +0000 Subject: [PATCH v3] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K In-Reply-To: <1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com> Message-ID: <56C72392.5010202@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 19/02/16 13:34, Thomas Petazzoni wrote: > This commits adds a new irqchip driver that handles the ODMI > controller found on Marvell 7K/8K processors. The ODMI controller > provide MSI interrupt functionality to on-board peripherals, much like > the GIC-v2m. > > Signed-off-by: Thomas Petazzoni > --- > Changes v2 -> v2: > - Express NODMIS_SHIFT, NODMIS_PER_FRAME, NODMIS_MASK in term of each > other. Suggested by Marc Zyngier. > - Rework the global bitmask allocation to make sure we allocate a > number of longs rather than a number of bytes, to avoid having the > bitmap API (which operates on longs) access memory we haven't > explicitly allocated. Reported by Marc Zyngier. > > Changes v1 -> v2: > - Better commit title, as suggested by Marc Zyngier. > - Improve the DT binding documentation, as suggested by Marc Zingier: > add a reference to the GIC documentation, be more specific about > the marvell,spi-base values, and add the requirement of the > interrupt-parent property. > - As suggested by Marc Zyngier, use a single global bitmap to > allocate all ODMIs, regardless of the frame they belong to. As part > of this change, the hwirq used to identify the interrupt inside the > ODMI irqdomain are 0-based (instead of being based on their > corresponding SPI base value), which allows to significantly > simplify the allocation/free logic. > --- > .../marvell,odmi-controller.txt | 41 ++++ > drivers/irqchip/Kconfig | 4 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-mvebu-odmi.c | 248 +++++++++++++++++++++ > 4 files changed, 294 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt > create mode 100644 drivers/irqchip/irq-mvebu-odmi.c Reviewed-by: Marc Zyngier I'll queue that for 4.6. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1949002AbcBSOPy (ORCPT ); Fri, 19 Feb 2016 09:15:54 -0500 Received: from foss.arm.com ([217.140.101.70]:46244 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2993019AbcBSOPu (ORCPT ); Fri, 19 Feb 2016 09:15:50 -0500 Subject: Re: [PATCH v3] irqchip: irq-mvebu-odmi: new driver for platform MSI on Marvell 7K/8K To: Thomas Petazzoni , Thomas Gleixner , Jason Cooper , linux-kernel@vger.kernel.org References: <1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org, Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , Nadav Haklai , Lior Amsalem From: Marc Zyngier Organization: ARM Ltd Message-ID: <56C72392.5010202@arm.com> Date: Fri, 19 Feb 2016 14:15:46 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.5.0 MIME-Version: 1.0 In-Reply-To: <1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/02/16 13:34, Thomas Petazzoni wrote: > This commits adds a new irqchip driver that handles the ODMI > controller found on Marvell 7K/8K processors. The ODMI controller > provide MSI interrupt functionality to on-board peripherals, much like > the GIC-v2m. > > Signed-off-by: Thomas Petazzoni > --- > Changes v2 -> v2: > - Express NODMIS_SHIFT, NODMIS_PER_FRAME, NODMIS_MASK in term of each > other. Suggested by Marc Zyngier. > - Rework the global bitmask allocation to make sure we allocate a > number of longs rather than a number of bytes, to avoid having the > bitmap API (which operates on longs) access memory we haven't > explicitly allocated. Reported by Marc Zyngier. > > Changes v1 -> v2: > - Better commit title, as suggested by Marc Zyngier. > - Improve the DT binding documentation, as suggested by Marc Zingier: > add a reference to the GIC documentation, be more specific about > the marvell,spi-base values, and add the requirement of the > interrupt-parent property. > - As suggested by Marc Zyngier, use a single global bitmap to > allocate all ODMIs, regardless of the frame they belong to. As part > of this change, the hwirq used to identify the interrupt inside the > ODMI irqdomain are 0-based (instead of being based on their > corresponding SPI base value), which allows to significantly > simplify the allocation/free logic. > --- > .../marvell,odmi-controller.txt | 41 ++++ > drivers/irqchip/Kconfig | 4 + > drivers/irqchip/Makefile | 1 + > drivers/irqchip/irq-mvebu-odmi.c | 248 +++++++++++++++++++++ > 4 files changed, 294 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt > create mode 100644 drivers/irqchip/irq-mvebu-odmi.c Reviewed-by: Marc Zyngier I'll queue that for 4.6. Thanks, M. -- Jazz is not dead. It just smells funny...