From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43310) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aXPGb-0003TL-BL for qemu-devel@nongnu.org; Sun, 21 Feb 2016 03:21:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aXPGY-0001nh-3Z for qemu-devel@nongnu.org; Sun, 21 Feb 2016 03:21:21 -0500 Received: from mout.web.de ([212.227.15.3]:59733) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aXPGX-0001mt-PJ for qemu-devel@nongnu.org; Sun, 21 Feb 2016 03:21:18 -0500 References: <1455736149-21869-1-git-send-email-davidkiarie4@gmail.com> <1455736149-21869-4-git-send-email-davidkiarie4@gmail.com> From: Jan Kiszka Message-ID: <56C97378.9020208@web.de> Date: Sun, 21 Feb 2016 09:21:12 +0100 MIME-Version: 1.0 In-Reply-To: <1455736149-21869-4-git-send-email-davidkiarie4@gmail.com> Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="krXdHtiIFwLEUQsf3CxBf5fARdEpcLV79" Subject: Re: [Qemu-devel] [V4 3/4] hw/i386: ACPI table for AMD IO MMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Kiarie , qemu-devel@nongnu.org Cc: marcel@redhat.com, valentine.sinitsyn@gmail.com, crosthwaitepeter@gmail.com, mst@redhat.com This is an OpenPGP/MIME signed message (RFC 4880 and 3156) --krXdHtiIFwLEUQsf3CxBf5fARdEpcLV79 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: quoted-printable On 2016-02-17 20:09, David Kiarie wrote: > Add IVRS table for AMD IO MMU. Also reverve MMIO > region for IO MMU via ACPI >=20 > Signed-off-by: David Kiarie > --- > hw/i386/acpi-build.c | 98 +++++++++++++++++++++++++++++++++++++= +++----- > include/hw/acpi/acpi-defs.h | 55 +++++++++++++++++++++++++ > 2 files changed, 142 insertions(+), 11 deletions(-) >=20 > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 739cfa3..b8cd091 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -51,6 +51,7 @@ > #include "hw/pci/pci_bus.h" > #include "hw/pci-host/q35.h" > #include "hw/i386/intel_iommu.h" > +#include "hw/i386/amd_iommu.h" > #include "hw/timer/hpet.h" > =20 > #include "hw/acpi/aml-build.h" > @@ -121,6 +122,12 @@ typedef struct AcpiBuildPciBusHotplugState { > bool pcihp_bridge_en; > } AcpiBuildPciBusHotplugState; > =20 > +typedef enum iommu_type { > + TYPE_AMD, > + TYPE_INTEL, > + TYPE_NONE > +} iommu_type; > + > static > int acpi_add_cpu_info(Object *o, void *opaque) > { > @@ -2423,6 +2430,78 @@ build_dmar_q35(GArray *table_data, GArray *linke= r) > } > =20 > static void > +build_amd_iommu(GArray *table_data, GArray *linker) > +{ > + int iommu_start =3D table_data->len; > + bool iommu_ambig; > + > + AcpiAMDIOMMUIVRS *ivrs; > + AcpiAMDIOMMUHardwareUnit *iommu; > + > + /* IVRS definition */ > + ivrs =3D acpi_data_push(table_data, sizeof(*ivrs)); > + ivrs->revision =3D cpu_to_le16(ACPI_IOMMU_IVRS_TYPE); > + ivrs->length =3D cpu_to_le16((sizeof(*ivrs) + sizeof(*iommu))); > + ivrs->v_common_info =3D cpu_to_le64(AMD_IOMMU_HOST_ADDRESS_WIDTH <= < 8); > + > + AMDIOMMUState *s =3D (AMDIOMMUState *)object_resolve_path_type("",= > + TYPE_AMD_IOMMU_DEVICE, &iommu_ambig); > + > + /* IVDB definition - type 10h */ > + iommu =3D acpi_data_push(table_data, sizeof(*iommu)); > + if (!iommu_ambig) { > + iommu->type =3D cpu_to_le16(0x10); > + /* IVHD flags */ > + iommu->flags =3D cpu_to_le16(iommu->flags); > + iommu->flags =3D cpu_to_le16(IVHD_HT_TUNEN | IVHD_PPRSUP | IVH= D_IOTLBSUP > + | IVHD_PREFSUP); > + iommu->length =3D cpu_to_le16(sizeof(*iommu)); > + iommu->device_id =3D cpu_to_le16(PCI_DEVICE_ID_RD890_IOMMU); > + iommu->capability_offset =3D cpu_to_le16(s->capab_offset); > + iommu->mmio_base =3D cpu_to_le64(s->mmio.addr); > + iommu->pci_segment =3D 0; > + iommu->interrupt_info =3D 0; > + /* EFR features */ > + iommu->efr_register =3D cpu_to_le64(IVHD_EFR_GTSUP | IVHD_EFR_= HATS > + | IVHD_EFR_GATS); > + iommu->efr_register =3D cpu_to_le64(iommu->efr_register); > + /* device entries */ > + memset(iommu->dev_entries, 0, 20); > + /* Add device flags here > + * This is are 4-byte device entries currently reporting the = range of > + * devices 00h - ffffh; all devices > + * > + * Device setting affecting all devices should be made here > + * > + * Refer to > + * (http://developer.amd.com/wordpress/media/2012/10/488821.p= df) > + * 5.2.2.1 > + */ > + iommu->dev_entries[12] =3D 3; > + iommu->dev_entries[16] =3D 4; > + iommu->dev_entries[17] =3D 0xff; > + iommu->dev_entries[18] =3D 0xff; > + } > + > + build_header(linker, table_data, (void *)(table_data->data + iommu= _start), > + "IVRS", table_data->len - iommu_start, 1, NULL); Requires rebasing over master (to append another NULL here). Jan --krXdHtiIFwLEUQsf3CxBf5fARdEpcLV79 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlbJc3gACgkQitSsb3rl5xRsvQCgoaljmxuLDl8prr60U0ZFHhyk 0nkAnRpXZKzXYsiltuGhUm6ScMdKOl5T =j2w1 -----END PGP SIGNATURE----- --krXdHtiIFwLEUQsf3CxBf5fARdEpcLV79--