On 2016-02-17 20:09, David Kiarie wrote: > Hello there, > > This is v5 of AMD IOMMU patches that fixes the issues mentioned in v4 except I fail to see the endian-ness issues Michael mentioned. > > I also stripped PIIX AMD IOMMU support since I added an MSI interrupt. One of the patches has a conflict with current master but it this is mergable I could quickly send a clean patch. I've just made it compile over master, but something is broken, at least in the PCI capability layout: # lspci -vv -s 00:04.0 00:04.0 Generic system peripheral [0806]: Advanced Micro Devices [AMD] Device 0020 Subsystem: Red Hat, Inc Device 1100 Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- Two times MSI, and a broken chain. At least unusual is also the reverted ordering. Please examine and fix. Thanks, Jan