From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50041) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aai15-0003vY-UE for qemu-devel@nongnu.org; Tue, 01 Mar 2016 05:59:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aai11-0002Kz-VE for qemu-devel@nongnu.org; Tue, 01 Mar 2016 05:58:59 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:35667) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aai11-0002KM-Q8 for qemu-devel@nongnu.org; Tue, 01 Mar 2016 05:58:55 -0500 References: <1456503598-27824-1-git-send-email-leon.alrae@imgtec.com> <1456503598-27824-2-git-send-email-leon.alrae@imgtec.com> From: Leon Alrae Message-ID: <56D575EA.3010008@imgtec.com> Date: Tue, 1 Mar 2016 10:58:50 +0000 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] hw/mips: add initial Cluster Power Controller support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers , Aurelien Jarno On 26/02/16 16:49, Peter Maydell wrote: > On 26 February 2016 at 16:19, Leon Alrae wrote: >> Cluster Power Controller (CPC) is responsible for power management in >> multiprocessing system. It provides registers to control the power and the >> clock frequency of the individual elements in the system. >> >> This patch implements only three registers that are used to control the >> power state of each VP on a single core: >> * VP Run is a write-only register used to set each VP to the run state >> * VP Stop is a write-only register used to set each VP to the suspend state >> * VP Running is a read-only register indicating the run state of each VP >> >> Signed-off-by: Leon Alrae >> --- >> default-configs/mips-softmmu.mak | 1 + >> default-configs/mips64-softmmu.mak | 1 + >> default-configs/mips64el-softmmu.mak | 1 + >> default-configs/mipsel-softmmu.mak | 1 + > > A separate thing, but maybe it would be worth having a mips-softmmu-common.mak > that all the mips*-softmmu.mak include to avoid having to repeat CONFIG defines > in four places like this. Good idea. I'll prepare a separate patch for that. And the comments below will be addressed in v2 (it'll also include few extra changes). Thanks, Leon > >> +static void mips_cpc_init(Object *obj) >> +{ >> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); >> + MIPSCPCState *s = MIPS_CPC(obj); >> + >> + memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc", >> + CPC_ADDRSPACE_SZ); >> + sysbus_init_mmio(sbd, &s->mr); >> +} >> + >> +static const TypeInfo mips_cpc_info = { >> + .name = TYPE_MIPS_CPC, >> + .parent = TYPE_SYS_BUS_DEVICE, >> + .instance_size = sizeof(MIPSCPCState), >> + .instance_init = mips_cpc_init, >> +}; > > I suspect you need a reset method. > >> + >> +static void mips_cpc_register_types(void) >> +{ >> + type_register_static(&mips_cpc_info); >> +} >> + >> +type_init(mips_cpc_register_types) > >> +typedef struct MIPSCPCState { >> + SysBusDevice parent_obj; >> + >> + MemoryRegion mr; >> + uint64_t vp_running; /* Indicates which VP's are in the run state */ > > This is state, so you need a VMState structure to migrate it correctly. > >> +} MIPSCPCState; >> + >> +#endif /* MIPS_CPC_H */ >> -- >> 2.1.0 > > thanks > -- PMM >