From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <JBeulich@suse.com>,
xen-devel <xen-devel@lists.xenproject.org>
Cc: Keir Fraser <keir@xen.org>, Wei Liu <wei.liu2@citrix.com>,
Tim Deegan <tim@xen.org>
Subject: Re: [PATCH 4/6] x86/HVM: limit flushing on cache attribute pinning adjustments
Date: Thu, 3 Mar 2016 17:38:02 +0000 [thread overview]
Message-ID: <56D8767A.8010201@citrix.com> (raw)
In-Reply-To: <56D8766F02000078000D8F4E@prv-mh.provo.novell.com>
On 03/03/16 16:37, Jan Beulich wrote:
> Avoid cache flush on EPT when removing a UC- range, since when used
> this type gets converted to UC anyway (there's no UC- among the types
> valid in MTRRs and hence EPT's emt field).
>
> We might further wwant to consider only forcing write buffer flushes
> when removing WC ranges.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
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next prev parent reply other threads:[~2016-03-03 17:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-03 16:28 [PATCH 0/6] x86/HVM: cache attribute pinning adjustments Jan Beulich
2016-03-03 16:33 ` [PATCH 1/6] x86/HVM: honor cache attribute pinning for RAM only Jan Beulich
2016-03-03 17:36 ` Andrew Cooper
2016-03-03 16:36 ` [PATCH 2/6] x86/HVM: remove unnecessary indirection from hvm_get_mem_pinned_cacheattr() Jan Beulich
2016-03-03 16:59 ` Wei Liu
2016-03-03 17:07 ` Wei Liu
2016-03-03 17:35 ` Andrew Cooper
2016-03-03 16:37 ` [PATCH 3/6] x86/HVM: adjust hvm_set_mem_pinned_cacheattr() error indications Jan Beulich
2016-03-03 17:37 ` Andrew Cooper
2016-03-03 16:37 ` [PATCH 4/6] x86/HVM: limit flushing on cache attribute pinning adjustments Jan Beulich
2016-03-03 17:38 ` Andrew Cooper [this message]
2016-03-03 16:38 ` [PATCH 5/6] x86/HVM: adjust hvm_get_mem_pinned_cacheattr() GFN parameter Jan Beulich
2016-03-03 17:39 ` Andrew Cooper
2016-03-03 16:38 ` [PATCH 6/6] x86/HVM: re-format cache attribute pinning code Jan Beulich
2016-03-03 17:40 ` Andrew Cooper
2016-03-04 10:36 ` [PATCH 0/6] x86/HVM: cache attribute pinning adjustments Tim Deegan
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