From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
To: Huacai Chen <chenhc@lemote.com>, Ralf Baechle <ralf@linux-mips.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>,
"Steven J . Hill" <Steven.Hill@imgtec.com>,
linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>
Subject: Re: [PATCH 1/3] MIPS: Reserve nosave data for hibernation
Date: Sun, 6 Mar 2016 15:17:08 +0300 [thread overview]
Message-ID: <56DC1FC4.7020007@cogentembedded.com> (raw)
In-Reply-To: <1457236202-16321-1-git-send-email-chenhc@lemote.com>
Hello.
On 3/6/2016 6:50 AM, Huacai Chen wrote:
> After commit 92923ca3aacef63c92dc (mm: meminit: only set page reserved
> in the memblock region), the MIPS hibernation is broken. Because pages
scripts/checkpatch.pl now enforces certain commit citing style, yours
doesn't quite match it...
> in nosave data section should be "reserved", but currently they aren't
> set to "reserved" at initialization. This patch makes hibernation work
> again.
>
> Signed-off-by: Huacai Chen <chenhc@lemote.com>
[...]
MBR, Sergei
prev parent reply other threads:[~2016-03-06 12:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-06 3:50 [PATCH 1/3] MIPS: Reserve nosave data for hibernation Huacai Chen
2016-03-06 3:50 ` [PATCH 2/3] MIPS: Loongson-3: Fix build error after ld-version.sh modification Huacai Chen
2016-03-06 12:18 ` Sergei Shtylyov
2016-03-06 3:50 ` [PATCH 3/3] MIPS: Loongson-3: Adjust irq dispatch to speedup processing Huacai Chen
2016-03-06 12:17 ` Sergei Shtylyov [this message]
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