Re: [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits

From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: tim.gore@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: implement WaClearTdlStateAckDirtyBits
Date: Wed, 9 Mar 2016 17:06:42 +0000	[thread overview]
Message-ID: <56E05822.3020208@linux.intel.com> (raw)
In-Reply-To: <1457541968-2004-1-git-send-email-tim.gore@intel.com>

On 09/03/2016 16:46, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
>
> This is to fix a GPU hang seen with mid thread pre-emption
> and pooled EUs.
>
> Signed-off-by: Tim Gore <tim.gore@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h  | 12 ++++++++++++
>   drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++++++++++++++
>   2 files changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7dfc400..0600bc7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1777,6 +1777,18 @@ enum skl_disp_power_wells {
>   #define   GEN9_IZ_HASHING_MASK(slice)			(0x3 << ((slice) * 2))
>   #define   GEN9_IZ_HASHING(slice, val)			((val) << ((slice) * 2))
>
> +/* WaClearTdlStateAckDirtyBits */
> +#define GEN8_STATE_ACK		0x20F0
> +#define GEN9_STATE_ACK_SLICE1	0x20F8
> +#define GEN9_STATE_ACK_SLICE2	0x2100

_MMIO(reg_addr)

regards
Arun

> +#define   GEN9_STATE_ACK_TDL0 (1 << 12)
> +#define   GEN9_STATE_ACK_TDL1 (1 << 13)
> +#define   GEN9_STATE_ACK_TDL2 (1 << 14)
> +#define   GEN9_STATE_ACK_TDL3 (1 << 15)
> +#define   GEN9_SUBSLICE_TDL_ACK_BITS \
> +	(GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \
> +	 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0)
> +
>   #define GFX_MODE	_MMIO(0x2520)
>   #define GFX_MODE_GEN7	_MMIO(0x229c)
>   #define RING_MODE_GEN7(ring)	_MMIO((ring)->mmio_base+0x29c)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 6fcbf6b..c36398d 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1447,6 +1447,25 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
>   		wa_ctx_emit(batch, index, MI_NOOP);
>   	}
>
> +	/* WaClearTdlStateAckDirtyBits:bxt */
> +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) <= BXT_REVID_B0)) {
> +		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
> +
> +		wa_ctx_emit(batch, index, GEN8_STATE_ACK);
> +		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
> +
> +		wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE1);
> +		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
> +
> +		wa_ctx_emit(batch, index, GEN9_STATE_ACK_SLICE2);
> +		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
> +
> +		wa_ctx_emit(batch, index, GEN7_ROW_CHICKEN2);
> +		/* dummy write to CS, mask bits are 0 to ensure the register is not modified */
> +		wa_ctx_emit(batch, index, 0x0);
> +		wa_ctx_emit(batch, index, MI_NOOP);
> +	}
> +
>   	/* WaDisableCtxRestoreArbitration:skl,bxt */
>   	if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
>   	    IS_BXT_REVID(dev, 0, BXT_REVID_A1))
>

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