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Subject: Re: iMX6q PCIe phy link never came up on kernel v4.4.x
To: Lucas Stach <l.stach@pengutronix.de>
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Cc: Richard Zhu <hongxing.zhu@nxp.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
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	Richard Zhu <Richard.Zhu@freescale.com>,
	Fabio Estevam <festevam@gmail.com>
From: Roberto Fichera <kernel@tekno-soft.it>
Message-ID: <56E1B04A.9010206@tekno-soft.it>
Date: Thu, 10 Mar 2016 18:35:06 +0100
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On 03/08/2016 03:53 PM, Lucas Stach wrote:
> Am Dienstag, den 08.03.2016, 15:39 +0100 schrieb Roberto Fichera:
>> > On 03/03/2016 07:34 PM, Roberto Fichera wrote:
>>> > > On 03/03/2016 03:34 PM, Roberto Fichera wrote:
>>> > >
>>> > > I've also checked clock, pll, PMU_MISC1 and CCGR[45] registers, all looks fine
>>> > > and exactly equal to uboot settings.
>>> > >
>>> > > However I'm investigating a possible HW issue in the LDVS pad wiring against
>>> > > the bridge XIO2001. Let's see once this is also clarified.
>> > 
>> > Our HW engineer has applied a fix to LVDS vs XIO2001 clock wiring. However I'm still getting the same problem.
>> > 
>> > I've tried to boot a kernel with uboot not setting up the PCIe subsys and below there is the resulting kernel log.
>> > Note that the CCGR5 doesn't set the CG2 field associated to sata_clk_enable. I think this field should be set all 1 to
>> > enable the SATA ref at 100MHz, right?
>> > 
> No, the reference manual is a bit confusing about this, but the LVDS1
> clock output is driven by sata_ref_100mhz, not the sata_clk gate.
>
> So the only thing that needs to be enabled for LVDS clock output is the
> 100MHz clock output from PLL ENET. (Register CCM_ANALOG_PLL_ENETn bit
> 20).

Guys! No more idea where to look at! Still getting PCIe link reaching L0 state under
uboot but doesn't progress more than POLL_ACTIVE or POLL_COMPLIANCE states
under kernel.

Any idea what to do?

Cheers,
Roberto Fichera.