From: Julien Grall <julien.grall@arm.com>
To: Shanker Donthineni <shankerd@codeaurora.org>,
Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
xen-devel@lists.xensource.com
Cc: Philip Elcan <pelcan@codeaurora.org>,
Ian Campbell <ian.campbell@citrix.com>,
Vikram Sethi <vikrams@codeaurora.org>
Subject: Re: [PATCH] xen/arm64: Fix incorrect memory region size in TCR2_EL2
Date: Sat, 12 Mar 2016 20:13:57 +0700 [thread overview]
Message-ID: <56E41615.6040006@arm.com> (raw)
In-Reply-To: <1457645293-4625-1-git-send-email-shankerd@codeaurora.org>
Hi Shanker,
On 11/03/2016 04:28, Shanker Donthineni wrote:
> The maximum and minimum values for T0SZ depend on level of
> translation as per AArch64 Virtual Memory System Architecture.
> The current code sets T0SZ to zero in TCR2_EL2 which is not
s/TCR2_EL2/TCR_EL2/
> valid and also might see unexpected behavior on some CPUs.
Can you provide more details?
I looked at the specification, programming the field T0SZ to 0 is valid
(see D4-1463 ARM DDI 0487A.b):
"For a stage 1 translation
The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller
than 16 then the implementation behaves as if the field were programmed
to 16 for all purposes other than reading back the value of the field."
> This patch sets T0SZ to (64-48)bits since XEN uses all 4 levels
> to cover 48bit (256TB) virtual address space.
>
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> ---
> xen/arch/arm/arm64/head.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index 19fa2bb..28ee404 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -343,7 +343,7 @@ skip_bss:
> * PT walks use Inner-Shareable accesses,
> * PT walks are write-back, write-allocate in both cache levels,
> * Full 64-bit address space goes through this table. */
This comment is no longer valid with your changes. Please update it.
> - ldr x0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0))
> + ldr x0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(64-48))
> /* ID_AA64MMFR0_EL1[3:0] (PARange) corresponds to TCR_EL2[18:16] (PS) */
> mrs x1, ID_AA64MMFR0_EL1
> bfi x0, x1, #16, #3
>
Regards,
--
Julien Grall
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next prev parent reply other threads:[~2016-03-12 13:13 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-10 21:28 [PATCH] xen/arm64: Fix incorrect memory region size in TCR2_EL2 Shanker Donthineni
2016-03-12 13:13 ` Julien Grall [this message]
2016-03-14 14:37 ` Shanker Donthineni
2016-03-14 14:58 ` Julien Grall
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