From mboxrd@z Thu Jan  1 00:00:00 1970
From: John Hsu <KCHSU0@nuvoton.com>
Subject: Re: [PATCH] ASoC: nau8825: fix interrupt fails and
 unstable after resume
Date: Tue, 15 Mar 2016 15:53:03 +0800
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 <20160301032623.GH18327@sirena.org.uk> <56E1105E.8010604@nuvoton.com>
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Hi,

On 3/10/2016 2:12 PM, John Hsu wrote:
>>>      regcache_cache_only(nau8825->regmap, false);
>>> -    regcache_sync(nau8825->regmap);
>>> -    enable_irq(client->irq);
>>> +    enable_irq(nau8825->irq);
>>>     
>>
>> We're removing the register cache sync here but I don't see us adding it
>> anywhere else.
>>   
> A part of suspend and resume action moves to set bias function, 
> nau8825_set_bias_level.
> We make register cache dirty in bias off; and make register cache sync 
> after resume in bias standby.
>
Just confirm it. Could you accept the explain about the register cache sync?
We need to change it or not? Very appreciate.