From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulpanit Subject: Re: [PART1 RFC v2 05/10] KVM: x86: Detect and Initialize AVIC support Date: Wed, 16 Mar 2016 15:21:39 +0700 Message-ID: <56E91793.90904@amd.com> References: <1457124368-2025-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1457124368-2025-6-git-send-email-Suravee.Suthikulpanit@amd.com> <56DDAF2D.3060703@redhat.com> <56E841CC.4090806@amd.com> <56E844E2.6090507@redhat.com> <56E8FB8B.7050700@amd.com> <56E90943.3060100@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Cc: , , , To: Paolo Bonzini , , , , , Return-path: In-Reply-To: <56E90943.3060100@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org Hi, On 03/16/2016 02:20 PM, Paolo Bonzini wrote: > > On 16/03/2016 07:22, Suravee Suthikulpanit wrote: >> >This is mainly causing a large number of VMEXIT due to NPF. > Got it, it's here in the manual: "System software is responsible for > setting up a translation in the nested page table granting guest read > and write permissions for accesses to the vAPIC Backing Page in SPA > space. AVIC hardware walks the nested page table to check permissions, > but does not use the SPA address specified in the leaf page table entry. > Instead, AVIC hardware finds this address in the AVIC_BACKING_PAGE > pointer field of the VMCB". > > Strictly speaking the address of the 0xFEE00000 translation is > unnecessary and it could be all zeroes, but I suggest that you set up an > APIC access page like Intel does (4k only), using the special memslot. > The AVIC backing page can then point to lapic->regs. > > Thanks for the explanation! > > Paolo > Ahh... you are right, this works also. Thanks for the pointer. I'm fixing this, doing some more testing, and cleaning up the code. This has simplify the init logic quite a bit. Thanks for suggestion, Suravee