From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32923) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ag8uR-0004xr-Sk for qemu-devel@nongnu.org; Wed, 16 Mar 2016 06:42:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ag8uO-0008Md-Hw for qemu-devel@nongnu.org; Wed, 16 Mar 2016 06:42:35 -0400 References: <1458121432-2855-1-git-send-email-lvivier@redhat.com> <56E92C01.1030600@suse.de> <56E92FE4.2070606@redhat.com> <56E93033.1040305@suse.de> <56E93621.1070304@redhat.com> From: Alexander Graf Message-ID: <56E93895.40501@suse.de> Date: Wed, 16 Mar 2016 11:42:29 +0100 MIME-Version: 1.0 In-Reply-To: <56E93621.1070304@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] ppc64: set MSR_SF bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas Huth , Laurent Vivier Cc: dgibson@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 16.03.16 11:32, Thomas Huth wrote: > On 16.03.2016 11:06, Alexander Graf wrote: >> >> >> On 16.03.16 11:05, Laurent Vivier wrote: >>> On 16/03/2016 10:48, Alexander Graf wrote: >>>> >>>> >>>> On 16.03.16 10:43, Laurent Vivier wrote: >>>>> When a qemu-system-ppc64 is started, the 64-bit mode bit >>>>> is not set in MSR. >>>>> >>>>> Signed-off-by: Laurent Vivier >>>> >>>> I guess commit 2cf3eb6df552cee74b52de9989e270b74e42847e broke this. = I'm >>>> surprised it didn't cause us more problems :). >>> >>> Linux kernel is ready to manage that: see enable_64b_mode in >>> arch/powerpc/kernel/head_64.S >> >> We don't boot Linux directly though, only openBIOS and SLOF :). >=20 > Both, SLOF and OpenBIOS, seem to enable the SF bit manually, too, see: >=20 > https://github.com/qemu/openbios/blob/master/arch/ppc/qemu/start.S#L524 >=20 > https://github.com/aik/SLOF/blob/master/board-qemu/llfw/startup.S#L91 Power up is slightly tricky, as machine state is pushed into the CPU from the outside FWIW. I think we're "cleanest" if we just consider power up a reset. Reset is properly defined as an exception (0x100). For exceptions, the 970MP user manual for example says: 4.5 Exception Definitions When an exception/interrupt is taken, all bits in the MSR are set to =E2=80=980=E2=80=99, with the following exceptions: =E2=80=A2 Exceptions always set MSR[SF] to =E2=80=981=E2=80=99. So the qemu fix is the correct one IMHO. Alex