From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs
Date: Thu, 17 Mar 2016 04:44:54 +0100 [thread overview]
Message-ID: <56EA2836.6050601@denx.de> (raw)
In-Reply-To: <BLU436-SMTP185E3E47537335D0CBF7E84FF8B0@phx.gbl>
On 03/17/2016 04:39 AM, Wills Wang wrote:
>
>
> On Thursday, March 17, 2016 05:35 AM, Marek Vasut wrote:
>> On 03/16/2016 09:59 AM, Wills Wang wrote:
>>> This patch add some common code for QCA/Atheros ath79 SOCs such as
>>> DDR tuning, chip reset and CPU detection.
>>>
>>> Signed-off-by: Wills Wang <wills.wang@live.com>
>>> ---
>>>
>>> Changes in v8:
>>> - Use setbits_be32
>>> - Use lookup-table instead of big switch statement for CPU detection
>>>
>> Good stuff, minor nits below.
[...]
>>> +phys_size_t initdram(int board_type)
>>> +{
>>> + ddr_tap_tuning();
>> Is the DDR tap tuning needed on all AR7xxx/AR9xxx systems ?
> Yes, it's for optimizing DDR timing according to hardware.
> Sometimes, the hard code value is not ideal.
AR934x doesn't seem to need this.
>>> + return get_ram_size((void *)KSEG1, SZ_256M);
>>> +}
>>> diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> new file mode 100644
>>> index 0000000..893dedc
>>> --- /dev/null
>>> +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
>>> @@ -0,0 +1,1184 @@
>>> +/*
>>> + * Atheros AR71XX/AR724X/AR913X SoC register definitions
>>> + *
>>> + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
>>> + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
>>> + * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
>>> + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#ifndef __ASM_MACH_AR71XX_REGS_H
>>> +#define __ASM_MACH_AR71XX_REGS_H
>>> +
>>> +#ifndef __ASSEMBLY__
>>> +#include <linux/bitops.h>
>>> +#else
>>> +#ifndef BIT
>>> +#define BIT(nr) (1 << (nr))
>> This should really go into some common header.
> This header is also included by some assembly code,
> but the BIT macro in linux/bitops.h isn't compatiable with assembler.
Because of the 1UL in it ?
[...]
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2016-03-17 3:44 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1458118800-23675-1-git-send-email-wills.wang@live.com>
2016-03-16 8:59 ` [U-Boot] [PATCH v8 1/9] mips: add base support for QCA/Atheros ath79 SOCs Wills Wang
2016-03-16 21:35 ` Marek Vasut
2016-03-17 3:39 ` Wills Wang
2016-03-17 3:44 ` Marek Vasut [this message]
2016-03-17 4:02 ` Wills Wang
2016-03-17 12:20 ` Marek Vasut
2016-03-17 12:35 ` Wills Wang
2016-03-17 12:37 ` Marek Vasut
2016-04-02 22:51 ` Marek Vasut
2016-03-17 12:48 ` Daniel Schwierzeck
2016-03-17 12:51 ` Marek Vasut
2016-04-10 18:35 ` Daniel Schwierzeck
2016-03-16 8:59 ` [U-Boot] [PATCH v8 2/9] mips: ath79: add support for AR933x SOCs Wills Wang
2016-03-16 21:38 ` Marek Vasut
2016-03-17 3:14 ` Wills Wang
2016-03-16 8:59 ` [U-Boot] [PATCH v8 3/9] mips: ath79: add support for QCA953x SOCs Wills Wang
2016-03-16 21:39 ` Marek Vasut
2016-03-17 3:14 ` Wills Wang
2016-03-17 3:27 ` Marek Vasut
2016-03-16 8:59 ` [U-Boot] [PATCH v8 4/9] drivers: pinctrl: Add simple pinctrl driver for QCA/Athores ar933x Wills Wang
2016-04-09 18:34 ` Simon Glass
2016-03-16 8:59 ` [U-Boot] [PATCH v8 5/9] drivers: pinctrl: Add simple pinctrl driver for QCA/Athores qca953x Wills Wang
2016-04-09 18:34 ` Simon Glass
2016-03-16 8:59 ` [U-Boot] [PATCH v8 6/9] drivers: serial: add serial driver for ar933x SOC Wills Wang
2016-04-09 18:34 ` Simon Glass
2016-04-11 7:57 ` Wills Wang
2016-04-11 13:41 ` Marek Vasut
2016-03-16 8:59 ` [U-Boot] [PATCH v8 7/9] drivers: spi: add spi support for QCA/Atheros ath79 SOCs Wills Wang
2016-03-16 8:59 ` [U-Boot] [PATCH v8 8/9] mips: ath79: add AP121 reference board Wills Wang
2016-03-16 9:00 ` [U-Boot] [PATCH v8 9/9] mips: ath79: add AP143 " Wills Wang
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