From mboxrd@z Thu Jan  1 00:00:00 1970
From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Subject: Re: [PART1 RFC v2 07/10] svm: Add VMEXIT handlers for AVIC
Date: Thu, 17 Mar 2016 10:58:07 +0700
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Hi Radim,

On 03/10/2016 03:55 AM, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote:
>> >+	pr_debug("%s: offset=3D%#x, rw=3D%#x, vector=3D%#x, vcpu_id=3D%#x=
, cpu=3D%#x\n",
>> >+		 __func__, offset, rw, vector, svm->vcpu.vcpu_id, svm->vcpu.cpu)=
;
>> >+
>> >+	BUG_ON(offset >=3D 0x400);
> These are valid faulting registers, so our implementation has to hand=
le
> them.  (And the rule is to never BUG if a recovery is simple.)
>

Just want to clarify the part that you mentioned "to handle them".=20
IIUC, offet 0x400 and above are for x2APIC stuff, which AVIC does not=20
currently support. Also, since I have only advertised as xAPIC when=20
enabling AVIC, if we run into the situation that the VM is trying to=20
access these register, we should just ignore it (and not BUG). Do I=20
understand that correctly?

Thanks,
Suravee