From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: tim.gore@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave
Date: Thu, 17 Mar 2016 10:21:06 +0000 [thread overview]
Message-ID: <56EA8512.50803@linux.intel.com> (raw)
In-Reply-To: <1458144826-17269-1-git-send-email-tim.gore@intel.com>
On 16/03/2016 16:13, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
>
> This allows writes to EU flow control registers. Together
> with SIP code from the user-mode driver this resolves a
> hang seen in some pre-emption scenarios. Note that this
> patch is just the kernel mode part of this workaround.
>
> v2. Oops, add FLOW_CONTROL_ENABLE macro to i915_reg.h.
>
> Signed-off-by: Tim Gore <tim.gore@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 85ceec6..adab0f0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7103,6 +7103,7 @@ enum skl_disp_power_wells {
> #define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3)
>
> #define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
> +#define FLOW_CONTROL_ENABLE (1<<15)
> #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
> #define STALL_DOP_GATING_DISABLE (1<<5)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 015dc7d..b6f6b3b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -925,8 +925,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> ECOCHK_DIS_TLB);
>
> + /* WaClearFlowControlGpgpuContextSave:skl,bxt */
> /* WaDisablePartialInstShootdown:skl,bxt */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> + FLOW_CONTROL_ENABLE |
> PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>
> /* Syncing dependencies between camera and graphics:skl,bxt */
>
looks good to me,
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
regards
Arun
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prev parent reply other threads:[~2016-03-17 10:21 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-16 16:13 [PATCH v3] drm/i915/gen9: add WaClearFlowControlGpgpuContextSave tim.gore
2016-03-17 9:36 ` ✗ Fi.CI.BAT: failure for drm/i915/gen9: add WaClearFlowControlGpgpuContextSave (rev3) Patchwork
2016-03-17 10:57 ` Gore, Tim
2016-03-18 11:15 ` Tvrtko Ursulin
2016-03-17 10:21 ` Arun Siluvery [this message]
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