diff for duplicates of <56F89C38.5000107@rock-chips.com> diff --git a/a/1.txt b/N1/1.txt index 45c4fef..9e1de14 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,9 +1,9 @@ Hi Heiko, -On 2016年03月28日 07:52, Heiko Stübner wrote: +On 2016?03?28? 07:52, Heiko St?bner wrote: > Hi Xing, > -> Am Samstag, 26. März 2016, 14:37:54 schrieb Xing Zheng: +> Am Samstag, 26. M?rz 2016, 14:37:54 schrieb Xing Zheng: >> Add devicetree bindings for Rockchip cru which found on >> Rockchip SoCs. >> @@ -100,19 +100,19 @@ clock-output-names: >> + >> +Example: General Register Files >> + ->> + pmugrf: syscon@ff320000 { +>> + pmugrf: syscon at ff320000 { >> + compatible = "rockchip,rk3399-pmugrf", "syscon"; >> + reg =<0x0 0xff320000 0x0 0x1000>; >> + }; >> + ->> + grf: syscon@ff770000 { +>> + grf: syscon at ff770000 { >> + compatible = "rockchip,rk3399-grf", "syscon"; >> + reg =<0x0 0xff770000 0x0 0x10000>; >> + }; >> + >> +Example: Clock controller node: >> + ->> + pmucru: pmu-clock-controller@ff750000 { +>> + pmucru: pmu-clock-controller at ff750000 { >> + compatible = "rockchip,rk3399-pmucru"; >> + reg =<0x0 0xff750000 0x0 0x1000>; >> + rockchip,grf =<&pmugrf>; @@ -120,7 +120,7 @@ clock-output-names: >> + #reset-cells =<1>; >> + }; >> + ->> + cru: clock-controller@ff760000 { +>> + cru: clock-controller at ff760000 { >> + compatible = "rockchip,rk3399-cru"; >> + reg =<0x0 0xff760000 0x0 0x1000>; >> + rockchip,grf =<&grf>; @@ -135,7 +135,7 @@ Done. >> +Example: UART controller node that consumes the clock generated by the >> clock + controller: >> + ->> + uart0: serial@ff1a0000 { +>> + uart0: serial at ff1a0000 { >> + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; >> + reg =<0x0 0xff180000 0x0 0x100>; >> + clocks =<&cru SCLK_UART0>,<&cru PCLK_UART0>; diff --git a/a/content_digest b/N1/content_digest index 6b4316c..ab0c8ac 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,32 +1,18 @@ "ref\01458974276-10325-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01458974276-10325-3-git-send-email-zhengxing@rock-chips.com\0" "ref\01507551.YPleCY5ZQt@phil\0" - "From\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Subject\0Re: [PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller\0" + "From\0zhengxing@rock-chips.com (Xing Zheng)\0" + "Subject\0[PATCH v5 2/4] dt-bindings: add bindings for rk3399 clock controller\0" "Date\0Mon, 28 Mar 2016 10:51:36 +0800\0" - "To\0Heiko St\303\274bner <heiko@sntech.de>\0" - "Cc\0linux-rockchip@lists.infradead.org" - huangtao@rock-chips.com - jay.xu@rock-chips.com - elaine.zhang@rock-chips.com - dianders@chromium.org - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - Mark Rutland <mark.rutland@arm.com> - Ian Campbell <ijc+devicetree@hellion.org.uk> - Kumar Gala <galak@codeaurora.org> - Stephen Boyd <sboyd@codeaurora.org> - devicetree@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Heiko,\n" "\n" - "On 2016\345\271\26403\346\234\21028\346\227\245 07:52, Heiko St\303\274bner wrote:\n" + "On 2016?03?28? 07:52, Heiko St?bner wrote:\n" "> Hi Xing,\n" ">\n" - "> Am Samstag, 26. M\303\244rz 2016, 14:37:54 schrieb Xing Zheng:\n" + "> Am Samstag, 26. M?rz 2016, 14:37:54 schrieb Xing Zheng:\n" ">> Add devicetree bindings for Rockchip cru which found on\n" ">> Rockchip SoCs.\n" ">>\n" @@ -123,19 +109,19 @@ ">> +\n" ">> +Example: General Register Files\n" ">> +\n" - ">> +\tpmugrf: syscon@ff320000 {\n" + ">> +\tpmugrf: syscon at ff320000 {\n" ">> +\t\tcompatible = \"rockchip,rk3399-pmugrf\", \"syscon\";\n" ">> +\t\treg =<0x0 0xff320000 0x0 0x1000>;\n" ">> +\t};\n" ">> +\n" - ">> +\tgrf: syscon@ff770000 {\n" + ">> +\tgrf: syscon at ff770000 {\n" ">> +\t\tcompatible = \"rockchip,rk3399-grf\", \"syscon\";\n" ">> +\t\treg =<0x0 0xff770000 0x0 0x10000>;\n" ">> +\t};\n" ">> +\n" ">> +Example: Clock controller node:\n" ">> +\n" - ">> +\tpmucru: pmu-clock-controller@ff750000 {\n" + ">> +\tpmucru: pmu-clock-controller at ff750000 {\n" ">> +\t\tcompatible = \"rockchip,rk3399-pmucru\";\n" ">> +\t\treg =<0x0 0xff750000 0x0 0x1000>;\n" ">> +\t\trockchip,grf =<&pmugrf>;\n" @@ -143,7 +129,7 @@ ">> +\t\t#reset-cells =<1>;\n" ">> +\t};\n" ">> +\n" - ">> +\tcru: clock-controller@ff760000 {\n" + ">> +\tcru: clock-controller at ff760000 {\n" ">> +\t\tcompatible = \"rockchip,rk3399-cru\";\n" ">> +\t\treg =<0x0 0xff760000 0x0 0x1000>;\n" ">> +\t\trockchip,grf =<&grf>;\n" @@ -158,7 +144,7 @@ ">> +Example: UART controller node that consumes the clock generated by the\n" ">> clock + controller:\n" ">> +\n" - ">> +\tuart0: serial@ff1a0000 {\n" + ">> +\tuart0: serial at ff1a0000 {\n" ">> +\t\tcompatible = \"rockchip,rk3399-uart\", \"snps,dw-apb-uart\";\n" ">> +\t\treg =<0x0 0xff180000 0x0 0x100>;\n" ">> +\t\tclocks =<&cru SCLK_UART0>,<&cru PCLK_UART0>;\n" @@ -174,4 +160,4 @@ "-- \n" - Xing Zheng -cb9caf5193de5182e2b0e799ea9dacab812095a803e1286498eeada6f1597f8a +d8e2b44ab26dc72f2f09214af904ab7b459e2bab24dd0a73128060205024e7f8
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