From: Paolo Bonzini <pbonzini@redhat.com>
To: "Sergey Fedorov" <serge.fdrv@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>,
QEMU Developers <qemu-devel@nongnu.org>,
Sergey Fedorov <sergey.fedorov@linaro.org>,
Peter Crosthwaite <crosthwaite.peter@gmail.com>
Subject: Re: [Qemu-devel] tcg: reworking tb_invalidated_flag
Date: Thu, 31 Mar 2016 21:56:50 +0200 [thread overview]
Message-ID: <56FD8102.6050203@redhat.com> (raw)
In-Reply-To: <56FD7486.20707@gmail.com>
On 31/03/2016 21:03, Sergey Fedorov wrote:
> Looks like we have to ensure all vCPUs are out of translated code when
> doing TB patching either doing tb_add_jump() or tb_phys_invalidate().
> Did I missed something?
Almost all TCG targets have naturally aligned instructions, so that's
not a problem; we can assume that 32-bit writes are atomic, though
perhaps we can change them to atomic_set just to be safe.
Only s390 and x86 can have unaligned instructions. For x86 I suppose
you can use 1 to 3 byte nops so that the first byte of the jump ends up
at ip%4=3. For s390 you can do the same, I don't know the encoding of
the canonical nop but an "or 0,0" instruction can do and is 16 bits wide
(in this case instructions are 16-bit aligned so you'd want ip%4=2).
Paolo
next prev parent reply other threads:[~2016-03-31 19:57 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-30 17:08 [Qemu-devel] tcg: reworking tb_invalidated_flag Sergey Fedorov
2016-03-30 18:13 ` Paolo Bonzini
2016-03-31 13:14 ` Sergey Fedorov
2016-03-31 13:37 ` Alex Bennée
2016-03-31 14:06 ` Sergey Fedorov
2016-03-31 19:03 ` Sergey Fedorov
2016-03-31 19:56 ` Paolo Bonzini [this message]
2016-04-01 11:11 ` Alex Bennée
2016-04-01 11:23 ` Sergey Fedorov
2016-03-31 13:40 ` Paolo Bonzini
2016-03-31 14:35 ` Sergey Fedorov
2016-03-31 14:44 ` Paolo Bonzini
2016-03-30 19:08 ` Richard Henderson
2016-03-30 21:21 ` Sergey Fedorov
2016-03-31 10:48 ` Alex Bennée
2016-03-31 12:42 ` Sergey Fedorov
2016-03-31 16:25 ` Richard Henderson
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