diff for duplicates of <56c5f618269c75d5bff313dce44fd4887f7e70c3.camel@mediatek.com> diff --git a/N1/2.bin b/N1/2.bin new file mode 100644 index 0000000..1ccd710 --- /dev/null +++ b/N1/2.bin @@ -0,0 +1,157 @@ +<html><body><p> +<pre> +On Mon, 2025-02-17 at 06:04 +0000, CK Hu (胡俊光) wrote: +> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote: +> > Add MDP-RSZ component support for MT8196. +> >  +> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com> +> > --- +> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 +> > ++++++++++++++++++++++++ +> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 + +> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++ +> >  3 files changed, 27 insertions(+) +> >  +> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +> > index 7f09a8977965..65878d3fe8a9 100644 +> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +> > @@ -46,6 +46,10 @@ +> >  #define DSC_BYPASSBIT(4) +> >  #define DSC_UFOE_SELBIT(16) +> >   +> > +#define DISP_REG_MDP_RSZ_EN0x0000 +>  +> Do you config resizer in bypass mode so you need not to enable it? + +Yes, it's bypass mode +To use the hardware path for PQ, +we need set this resizer to bypass mode because the path mux design of +the MT8196 + +>  +> > +#define DISP_REG_MDP_RSZ_INPUT_SIZE0x0010 +> > +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE0x0014 +> > + +> >  #define DISP_REG_OD_EN0x0000 +> >  #define DISP_REG_OD_CFG0x0020 +> >  #define OD_RELAYMODEBIT(0) +> > @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev) +> >  writel(1, priv->regs + DISP_REG_OD_EN); +> >  } +> >   +> > +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w, +> > +       unsigned int h, unsigned int +> > vrefresh, +> > +       unsigned int bpc, struct cmdq_pkt +> > *cmdq_pkt) +> > +{ +> > +struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); +> > + +> > +mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, +> > +      DISP_REG_MDP_RSZ_INPUT_SIZE); +> > +mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, +> > +      DISP_REG_MDP_RSZ_OUTPUT_SIZE); +>  +> Do you config resizer in bypass mode so width and height is set to +> zero? + +Yes, we set resizer's width and height to 0 and use the bypass mode + +>  +> Regards, +> CK +>  +> > +} +> > + +> >  static void mtk_postmask_config(struct device *dev, unsigned int +> > w, +> >  unsigned int h, unsigned int +> > vrefresh, +> >  unsigned int bpc, struct cmdq_pkt +> > *cmdq_pkt) +> > @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs +> > ddp_ovlsys_adaptor = { +> >  .get_num_formats = mtk_ovlsys_adaptor_get_num_formats, +> >  }; +> >   +> > +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = { +> > +.clk_enable = mtk_ddp_clk_enable, +> > +.clk_disable = mtk_ddp_clk_disable, +> > +.config = mtk_mdp_rsz_config, +> > +}; +> > + +> >  static const struct mtk_ddp_comp_funcs ddp_postmask = { +> >  .clk_enable = mtk_ddp_clk_enable, +> >  .clk_disable = mtk_ddp_clk_disable, +> > @@ -454,6 +476,7 @@ static const char * const +> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { +> >  [MTK_DISP_DITHER] = "dither", +> >  [MTK_DISP_DSC] = "dsc", +> >  [MTK_DISP_GAMMA] = "gamma", +> > +[MTK_DISP_MDP_RSZ] = "mdp-rsz", +> >  [MTK_DISP_MERGE] = "merge", +> >  [MTK_DISP_MUTEX] = "mutex", +> >  [MTK_DISP_OD] = "od", +> > @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match +> > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] +> >  [DDP_COMPONENT_DSI2]= { +> > MTK_DSI,2, &ddp_dsi }, +> >  [DDP_COMPONENT_DSI3]= { +> > MTK_DSI,3, &ddp_dsi }, +> >  [DDP_COMPONENT_GAMMA]= { +> > MTK_DISP_GAMMA,0, &ddp_gamma }, +> > +[DDP_COMPONENT_MDP_RSZ0]= { +> > MTK_DISP_MDP_RSZ,0, &ddp_mdp_rsz}, +> >  [DDP_COMPONENT_MERGE0]= { +> > MTK_DISP_MERGE,0, &ddp_merge }, +> >  [DDP_COMPONENT_MERGE1]= { +> > MTK_DISP_MERGE,1, &ddp_merge }, +> >  [DDP_COMPONENT_MERGE2]= { +> > MTK_DISP_MERGE,2, &ddp_merge }, +> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +> > index badb42bd4f7c..87f573fcc903 100644 +> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type { +> >  MTK_DISP_OVLSYS_ADAPTOR, +> >  MTK_DISP_OVL_2L, +> >  MTK_DISP_OVL_ADAPTOR, +> > +MTK_DISP_MDP_RSZ, +> >  MTK_DISP_POSTMASK, +> >  MTK_DISP_PWM, +> >  MTK_DISP_RDMA, +> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> > index 50f5f81a7da1..b810a197f58b 100644 +> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c +> > @@ -885,6 +885,8 @@ static const struct of_device_id +> > mtk_ddp_comp_dt_ids[] = { +> >    .data = (void *)MTK_DISP_GAMMA, }, +> >  { .compatible = "mediatek,mt8195-disp-gamma", +> >    .data = (void *)MTK_DISP_GAMMA, }, +> > +{ .compatible = "mediatek,mt8196-disp-mdp-rsz", +> > +  .data = (void *)MTK_DISP_MDP_RSZ }, +> >  { .compatible = "mediatek,mt8195-disp-merge", +> >    .data = (void *)MTK_DISP_MERGE }, +> >  { .compatible = "mediatek,mt2701-disp-mutex", +>  + + +</pre> +</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ******************** +The information contained in this e-mail message (including any +attachments) may be confidential, proprietary, privileged, or otherwise +exempt from disclosure under applicable laws. It is intended to be +conveyed only to the designated recipient(s). Any use, dissemination, +distribution, printing, retaining or copying of this e-mail (including its +attachments) by unintended recipient(s) is strictly prohibited and may +be unlawful. If you are not an intended recipient of this e-mail, or believe +that you have received this e-mail in error, please notify the sender +immediately (by replying to this e-mail), delete any and all copies of +this e-mail (including any attachments) from your system, and do not +disclose the content of this e-mail to any other person. Thank you! +</pre><!--}--> diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..da1f671 --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,3 @@ +Content-Type: text/html; + charset="utf-8" +Content-Transfer-Encoding: base64 diff --git a/a/content_digest b/N1/content_digest index 60eb249..8d02c04 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -22,7 +22,7 @@ linux-mediatek@lists.infradead.org <linux-mediatek@lists.infradead.org> matthias.bgg@gmail.com <matthias.bgg@gmail.com> " p.zabel@pengutronix.de <p.zabel@pengutronix.de>\0" - "\00:1\0" + "\01:1\0" "b\0" "On Mon, 2025-02-17 at 06:04 +0000, CK Hu (\350\203\241\344\277\212\345\205\211) wrote:\n" "> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:\n" @@ -163,5 +163,164 @@ "> > \302\240\t\302\240 .data = (void *)MTK_DISP_MERGE },\n" "> > \302\240\t{ .compatible = \"mediatek,mt2701-disp-mutex\",\n" > + "\01:2\0" + "b\0" + "<html><body><p>\r\n" + "<pre>\r\n" + "On Mon, 2025-02-17 at 06:04 +0000, CK Hu (胡俊光) wrote:\r\n" + "> On Tue, 2025-02-11 at 10:52 +0800, Sunny Shen wrote:\r\n" + "> > Add MDP-RSZ component support for MT8196.\r\n" + "> > \r\n" + "> > Signed-off-by: Sunny Shen <sunny.shen@mediatek.com>\r\n" + "> > ---\r\n" + "> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24\r\n" + "> > ++++++++++++++++++++++++\r\n" + "> >  drivers/gpu/drm/mediatek/mtk_ddp_comp.h |  1 +\r\n" + "> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++\r\n" + "> >  3 files changed, 27 insertions(+)\r\n" + "> > \r\n" + "> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c\r\n" + "> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c\r\n" + "> > index 7f09a8977965..65878d3fe8a9 100644\r\n" + "> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c\r\n" + "> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c\r\n" + "> > @@ -46,6 +46,10 @@\r\n" + "> >  #define DSC_BYPASSBIT(4)\r\n" + "> >  #define DSC_UFOE_SELBIT(16)\r\n" + "> >  \r\n" + "> > +#define DISP_REG_MDP_RSZ_EN0x0000\r\n" + "> \r\n" + "> Do you config resizer in bypass mode so you need not to enable it?\r\n" + "\r\n" + "Yes, it's bypass mode\r\n" + "To use the hardware path for PQ,\r\n" + "we need set this resizer to bypass mode because the path mux design of\r\n" + "the MT8196\r\n" + "\r\n" + "> \r\n" + "> > +#define DISP_REG_MDP_RSZ_INPUT_SIZE0x0010\r\n" + "> > +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE0x0014\r\n" + "> > +\r\n" + "> >  #define DISP_REG_OD_EN0x0000\r\n" + "> >  #define DISP_REG_OD_CFG0x0020\r\n" + "> >  #define OD_RELAYMODEBIT(0)\r\n" + "> > @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev)\r\n" + "> >  writel(1, priv->regs + DISP_REG_OD_EN);\r\n" + "> >  }\r\n" + "> >  \r\n" + "> > +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w,\r\n" + "> > +       unsigned int h, unsigned int\r\n" + "> > vrefresh,\r\n" + "> > +       unsigned int bpc, struct cmdq_pkt\r\n" + "> > *cmdq_pkt)\r\n" + "> > +{\r\n" + "> > +struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);\r\n" + "> > +\r\n" + "> > +mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,\r\n" + "> > +      DISP_REG_MDP_RSZ_INPUT_SIZE);\r\n" + "> > +mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,\r\n" + "> > +      DISP_REG_MDP_RSZ_OUTPUT_SIZE);\r\n" + "> \r\n" + "> Do you config resizer in bypass mode so width and height is set to\r\n" + "> zero?\r\n" + "\r\n" + "Yes, we set resizer's width and height to 0 and use the bypass mode\r\n" + "\r\n" + "> \r\n" + "> Regards,\r\n" + "> CK\r\n" + "> \r\n" + "> > +}\r\n" + "> > +\r\n" + "> >  static void mtk_postmask_config(struct device *dev, unsigned int\r\n" + "> > w,\r\n" + "> >  unsigned int h, unsigned int\r\n" + "> > vrefresh,\r\n" + "> >  unsigned int bpc, struct cmdq_pkt\r\n" + "> > *cmdq_pkt)\r\n" + "> > @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs\r\n" + "> > ddp_ovlsys_adaptor = {\r\n" + "> >  .get_num_formats = mtk_ovlsys_adaptor_get_num_formats,\r\n" + "> >  };\r\n" + "> >  \r\n" + "> > +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz = {\r\n" + "> > +.clk_enable = mtk_ddp_clk_enable,\r\n" + "> > +.clk_disable = mtk_ddp_clk_disable,\r\n" + "> > +.config = mtk_mdp_rsz_config,\r\n" + "> > +};\r\n" + "> > +\r\n" + "> >  static const struct mtk_ddp_comp_funcs ddp_postmask = {\r\n" + "> >  .clk_enable = mtk_ddp_clk_enable,\r\n" + "> >  .clk_disable = mtk_ddp_clk_disable,\r\n" + "> > @@ -454,6 +476,7 @@ static const char * const\r\n" + "> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {\r\n" + "> >  [MTK_DISP_DITHER] = "dither",\r\n" + "> >  [MTK_DISP_DSC] = "dsc",\r\n" + "> >  [MTK_DISP_GAMMA] = "gamma",\r\n" + "> > +[MTK_DISP_MDP_RSZ] = "mdp-rsz",\r\n" + "> >  [MTK_DISP_MERGE] = "merge",\r\n" + "> >  [MTK_DISP_MUTEX] = "mutex",\r\n" + "> >  [MTK_DISP_OD] = "od",\r\n" + "> > @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match\r\n" + "> > mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]\r\n" + "> >  [DDP_COMPONENT_DSI2]= {\r\n" + "> > MTK_DSI,2, &ddp_dsi },\r\n" + "> >  [DDP_COMPONENT_DSI3]= {\r\n" + "> > MTK_DSI,3, &ddp_dsi },\r\n" + "> >  [DDP_COMPONENT_GAMMA]= {\r\n" + "> > MTK_DISP_GAMMA,0, &ddp_gamma },\r\n" + "> > +[DDP_COMPONENT_MDP_RSZ0]= {\r\n" + "> > MTK_DISP_MDP_RSZ,0, &ddp_mdp_rsz},\r\n" + "> >  [DDP_COMPONENT_MERGE0]= {\r\n" + "> > MTK_DISP_MERGE,0, &ddp_merge },\r\n" + "> >  [DDP_COMPONENT_MERGE1]= {\r\n" + "> > MTK_DISP_MERGE,1, &ddp_merge },\r\n" + "> >  [DDP_COMPONENT_MERGE2]= {\r\n" + "> > MTK_DISP_MERGE,2, &ddp_merge },\r\n" + "> > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h\r\n" + "> > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h\r\n" + "> > index badb42bd4f7c..87f573fcc903 100644\r\n" + "> > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h\r\n" + "> > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h\r\n" + "> > @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type {\r\n" + "> >  MTK_DISP_OVLSYS_ADAPTOR,\r\n" + "> >  MTK_DISP_OVL_2L,\r\n" + "> >  MTK_DISP_OVL_ADAPTOR,\r\n" + "> > +MTK_DISP_MDP_RSZ,\r\n" + "> >  MTK_DISP_POSTMASK,\r\n" + "> >  MTK_DISP_PWM,\r\n" + "> >  MTK_DISP_RDMA,\r\n" + "> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> > index 50f5f81a7da1..b810a197f58b 100644\r\n" + "> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c\r\n" + "> > @@ -885,6 +885,8 @@ static const struct of_device_id\r\n" + "> > mtk_ddp_comp_dt_ids[] = {\r\n" + "> >    .data = (void *)MTK_DISP_GAMMA, },\r\n" + "> >  { .compatible = "mediatek,mt8195-disp-gamma",\r\n" + "> >    .data = (void *)MTK_DISP_GAMMA, },\r\n" + "> > +{ .compatible = "mediatek,mt8196-disp-mdp-rsz",\r\n" + "> > +  .data = (void *)MTK_DISP_MDP_RSZ },\r\n" + "> >  { .compatible = "mediatek,mt8195-disp-merge",\r\n" + "> >    .data = (void *)MTK_DISP_MERGE },\r\n" + "> >  { .compatible = "mediatek,mt2701-disp-mutex",\r\n" + "> \r\n" + "\r\n" + "\r\n" + "</pre>\r\n" + "</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ********************\r\n" + "The information contained in this e-mail message (including any \r\n" + "attachments) may be confidential, proprietary, privileged, or otherwise\r\n" + "exempt from disclosure under applicable laws. It is intended to be \r\n" + "conveyed only to the designated recipient(s). Any use, dissemination, \r\n" + "distribution, printing, retaining or copying of this e-mail (including its \r\n" + "attachments) by unintended recipient(s) is strictly prohibited and may \r\n" + "be unlawful. If you are not an intended recipient of this e-mail, or believe \r\n" + "that you have received this e-mail in error, please notify the sender \r\n" + "immediately (by replying to this e-mail), delete any and all copies of \r\n" + "this e-mail (including any attachments) from your system, and do not\r\n" + "disclose the content of this e-mail to any other person. Thank you!\r\n" + </pre><!--}--> -da010e23f70081ee8bce53880c1cd10a1307b9e7f1c69608fef33f8dd9a6b4ab +c965187a387913fdcc82d724c37bda17eef7fe6b9eefceec2d751be7d7795e4e
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