From: Stephen Boyd <sboyd@kernel.org>
To: Marek Vasut <marek.vasut+renesas@mailbox.org>, linux-clk@vger.kernel.org
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>,
Biju Das <biju.das.jz@bp.renesas.com>,
Alexander Stein <alexander.stein@ew.tq-group.com>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v3 4/4] clk: rs9: Add support for 9FGV0841
Date: Sun, 17 Dec 2023 15:29:03 -0800 [thread overview]
Message-ID: <56e85ea5916d58720bedfb1f0dd1df39.sboyd@kernel.org> (raw)
In-Reply-To: <20231113221949.111964-4-marek.vasut+renesas@mailbox.org>
Quoting Marek Vasut (2023-11-13 14:18:54)
> This model is similar to 9FGV0441, the DIFx bits start at bit 0 again,
> except this chip has 8 outputs.
>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> ---
Applied to clk-next
next prev parent reply other threads:[~2023-12-17 23:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-13 22:18 [PATCH v3 1/4] dt-bindings: clk: rs9: Add 9FGV0841 Marek Vasut
2023-11-13 22:18 ` [PATCH v3 2/4] clk: rs9: Limit check to vendor ID in VID register Marek Vasut
2023-12-17 23:28 ` Stephen Boyd
2023-11-13 22:18 ` [PATCH v3 3/4] clk: rs9: Replace model check with bitshift from chip data Marek Vasut
2023-12-17 23:28 ` Stephen Boyd
2023-11-13 22:18 ` [PATCH v3 4/4] clk: rs9: Add support for 9FGV0841 Marek Vasut
2023-12-17 23:29 ` Stephen Boyd [this message]
2023-12-17 23:28 ` [PATCH v3 1/4] dt-bindings: clk: rs9: Add 9FGV0841 Stephen Boyd
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