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From: Alexander Graf <agraf@suse.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] Unaligned flush_dcache_range in axs101.c
Date: Mon, 4 Apr 2016 09:38:05 +0200	[thread overview]
Message-ID: <570219DD.4020007@suse.de> (raw)

Hi Alexey,

Marek just pointed out to me the fact that flush_dcache_range on arm
expects cache line aligned arguments. However, it seems like in axs101.c
we have an unaligned cache flush:

  flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));

Could you please verify whether this is correct and if not just send a
quick patch to fix it?


Thanks!

Alex

             reply	other threads:[~2016-04-04  7:38 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-04  7:38 Alexander Graf [this message]
2016-04-11 17:48 ` [U-Boot] Unaligned flush_dcache_range in axs101.c Alexey Brodkin
2016-04-11 17:54   ` Marek Vasut
2016-04-11 18:13     ` Alexey Brodkin
2016-04-11 18:48       ` Marek Vasut
2016-04-15 13:00         ` Alexey Brodkin
2016-04-15 13:49           ` Marek Vasut
2016-05-26 11:39             ` Alexey Brodkin
2016-05-26 11:39               ` [U-Boot] " Alexey Brodkin
2016-05-26 12:07               ` Vineet Gupta
2016-05-26 12:07                 ` [U-Boot] " Vineet Gupta
2016-05-27 13:21               ` Marek Vasut
2016-05-27 13:21                 ` [U-Boot] " Marek Vasut

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