Re: [Qemu-devel] best way to implement emulation of AArch64 tagged addresses

[Richard Henderson <rth@twiddle.net>]

On 04/04/2016 08:51 AM, Peter Maydell wrote:
> I thought of two possible ways to approach implementing this.
> Option (1) would be to change the codegen in translate-a64.c so that
> we mask out high bits before doing the QEMU load/store TCG op.
> Option (2) leaves the VA that we pass to the TCG load/store alone
> (ie with tag bits intact) and tries to handle this all in the va-to-pa
> code.
>
> I think option (1) is a non-starter because of that requirement to
> report the full address with tags in the FAR (as well as being slower
> due to all the extra masking on memory operations). So that leaves
> option (2), possibly with some help from common code to make things
> a bit less awkward.

Agreed.

> In particular I think if you just do the relevant handling of the tag
> bits in target-arm's get_phys_addr() and its subroutines then this
> should work ok, with the exceptions that:
>   * the QEMU TLB code will think that [tag A + address X] and
>     [tag B + address X] are different virtual addresses and they will
>     miss each other in the TLB

Yep.  Not only miss, but actively contend with each other.

>   * tlb invalidate by address becomes nasty because we need to invalidate
>     [every tag + address X]

Hmm.  We should require only one flush for X.  But the common code doesn't know 
that...  I suppose a new tlb_flush_page_mask would do the trick.

> Can we fix those just by having arm_tlb_fill() call
> tlb_set_page_with_attrs() with the vaddr with the tag masked out?

No, that misses when we perform the full vaddr+tag comparison on the TCG fast path.

> [NB: this is all assuming softmmu; getting tagged addresses to work
> in linux-user mode would require doing the masking in translate.c,
> but I definitely don't want two implementations so I guess we just
> ignore linux-user here.]

Let's just say it's another user for the oft wished for softmmu-in-linux-user.


r~