diff for duplicates of <570563D3.9080704@denx.de> diff --git a/a/1.txt b/N1/1.txt index a5e9ce0..eca1e12 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -9,7 +9,7 @@ Try with the attached patches, I am planning to use them for V11 submission. I think you're hitting the problem with missing buslock. > On 1/11/2016 10:04 AM, Marek Vasut wrote: ->> From: Graham Moore <grmoore@opensource.altera.com> +>> From: Graham Moore <grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> >> >> Add support for the Cadence QSPI controller. This controller is >> present in the Altera SoCFPGA SoCs and this driver has been tested diff --git a/a/2.txt b/N1/2.txt index 5b365cf..ce04e84 100644 --- a/a/2.txt +++ b/N1/2.txt @@ -1,5 +1,5 @@ >From 6a649c8263149b06d29a3acc91b63fb0c1728deb Mon Sep 17 00:00:00 2001 -From: Marek Vasut <marex@denx.de> +From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> Date: Wed, 23 Mar 2016 08:26:46 +0100 Subject: [PATCH 1/3] mtd: spi-nor: cqspi: Reinit completion during indirect read and write @@ -8,7 +8,7 @@ Reinit the completion structures when performing indirect I/O. This does not manifest as a bug, but is necessary to make the code fully correct. -Signed-off-by: Marek Vasut <marex@denx.de> +Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> --- drivers/mtd/spi-nor/cadence-quadspi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/a/3.txt b/N1/3.txt index 08391df..122e00e 100644 --- a/a/3.txt +++ b/N1/3.txt @@ -1,12 +1,12 @@ >From 30391427f34193d9229e70bf62794cbcb733b047 Mon Sep 17 00:00:00 2001 -From: Marek Vasut <marex@denx.de> +From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> Date: Wed, 23 Mar 2016 08:27:50 +0100 Subject: [PATCH 2/3] mtd: spi-nor: cqspi: Optimize the control reconfiguration Always disable and re-enable the controller only once when switching the chipselect and bus speed instead of doing so twice. -Signed-off-by: Marek Vasut <marex@denx.de> +Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> --- drivers/mtd/spi-nor/cadence-quadspi.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/a/4.txt b/N1/4.txt index e5dd101..49c3141 100644 --- a/a/4.txt +++ b/N1/4.txt @@ -1,5 +1,5 @@ >From e680fa497cf0e2f41fe1b56c7d6b868596d8e420 Mon Sep 17 00:00:00 2001 -From: Marek Vasut <marex@denx.de> +From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> Date: Wed, 23 Mar 2016 08:30:47 +0100 Subject: [PATCH 3/3] mtd: spi-nor: cqspi: Add bus lock @@ -11,7 +11,7 @@ only locks the mutex in struct spi_nor and therefore the locking happens with per-flash granularity, which is not enough to prevent concurrent access to the SPI NOR controller registers. -Signed-off-by: Marek Vasut <marex@denx.de> +Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org> --- drivers/mtd/spi-nor/cadence-quadspi.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/a/content_digest b/N1/content_digest index ce01a18..447d28c 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,20 @@ "ref\01452486886-8049-1-git-send-email-marex@denx.de\0" "ref\01452486886-8049-2-git-send-email-marex@denx.de\0" "ref\057053F81.70204@ti.com\0" - "From\0Marek Vasut <marex@denx.de>\0" + "ref\057053F81.70204-l0cyMroinI0@public.gmane.org\0" + "From\0Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\0" "Subject\0Re: [PATCH V10 2/2] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller.\0" "Date\0Wed, 06 Apr 2016 21:30:27 +0200\0" "To\0R" - Vignesh <vigneshr@ti.com> - " linux-mtd@lists.infradead.org\0" - "Cc\0Graham Moore <grmoore@opensource.altera.com>" - Alan Tull <atull@opensource.altera.com> - Brian Norris <computersforpeace@gmail.com> - David Woodhouse <dwmw2@infradead.org> - Dinh Nguyen <dinguyen@opensource.altera.com> - Yves Vandervennet <yvanderv@opensource.altera.com> - " devicetree@vger.kernel.org\0" + Vignesh <vigneshr-l0cyMroinI0@public.gmane.org> + " linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "Cc\0Graham Moore <grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>" + Alan Tull <atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> + Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + David Woodhouse <dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org> + Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> + Yves Vandervennet <yvanderv-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\01:1\0" "b\0" "On 04/06/2016 06:55 PM, R, Vignesh wrote:\n" @@ -27,7 +28,7 @@ "submission. I think you're hitting the problem with missing buslock.\n" "\n" "> On 1/11/2016 10:04 AM, Marek Vasut wrote:\n" - ">> From: Graham Moore <grmoore@opensource.altera.com>\n" + ">> From: Graham Moore <grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>\n" ">>\n" ">> Add support for the Cadence QSPI controller. This controller is\n" ">> present in the Altera SoCFPGA SoCs and this driver has been tested\n" @@ -120,7 +121,7 @@ "fn\00001-mtd-spi-nor-cqspi-Reinit-completion-during-indirect-.patch\0" "b\0" ">From 6a649c8263149b06d29a3acc91b63fb0c1728deb Mon Sep 17 00:00:00 2001\n" - "From: Marek Vasut <marex@denx.de>\n" + "From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\n" "Date: Wed, 23 Mar 2016 08:26:46 +0100\n" "Subject: [PATCH 1/3] mtd: spi-nor: cqspi: Reinit completion during indirect\n" " read and write\n" @@ -129,7 +130,7 @@ "does not manifest as a bug, but is necessary to make the code fully\n" "correct.\n" "\n" - "Signed-off-by: Marek Vasut <marex@denx.de>\n" + "Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\n" "---\n" " drivers/mtd/spi-nor/cadence-quadspi.c | 6 ++++++\n" " 1 file changed, 6 insertions(+)\n" @@ -164,14 +165,14 @@ "fn\00002-mtd-spi-nor-cqspi-Optimize-the-control-reconfigurati.patch\0" "b\0" ">From 30391427f34193d9229e70bf62794cbcb733b047 Mon Sep 17 00:00:00 2001\n" - "From: Marek Vasut <marex@denx.de>\n" + "From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\n" "Date: Wed, 23 Mar 2016 08:27:50 +0100\n" "Subject: [PATCH 2/3] mtd: spi-nor: cqspi: Optimize the control reconfiguration\n" "\n" "Always disable and re-enable the controller only once when switching\n" "the chipselect and bus speed instead of doing so twice.\n" "\n" - "Signed-off-by: Marek Vasut <marex@denx.de>\n" + "Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\n" "---\n" " drivers/mtd/spi-nor/cadence-quadspi.c | 18 ++++++++++--------\n" " 1 file changed, 10 insertions(+), 8 deletions(-)\n" @@ -238,7 +239,7 @@ "fn\00003-mtd-spi-nor-cqspi-Add-bus-lock.patch\0" "b\0" ">From e680fa497cf0e2f41fe1b56c7d6b868596d8e420 Mon Sep 17 00:00:00 2001\n" - "From: Marek Vasut <marex@denx.de>\n" + "From: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\n" "Date: Wed, 23 Mar 2016 08:30:47 +0100\n" "Subject: [PATCH 3/3] mtd: spi-nor: cqspi: Add bus lock\n" "\n" @@ -250,7 +251,7 @@ "happens with per-flash granularity, which is not enough to prevent\n" "concurrent access to the SPI NOR controller registers.\n" "\n" - "Signed-off-by: Marek Vasut <marex@denx.de>\n" + "Signed-off-by: Marek Vasut <marex-ynQEQJNshbs@public.gmane.org>\n" "---\n" " drivers/mtd/spi-nor/cadence-quadspi.c | 35 +++++++++++++++++++++++++++++------\n" " 1 file changed, 29 insertions(+), 6 deletions(-)\n" @@ -352,4 +353,4 @@ "-- \n" 2.7.0 -3fda975276743ab5c9128d1d194242cef8c560fc9d40c1383bc9b62d15cd5d53 +52fdf40b1d32fe9e11ea658cdbeff20324f0462584d653e741f528696b2afe7a
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