diff for duplicates of <570B50B4.4020304@nvidia.com>

diff --git a/a/1.txt b/N1/1.txt
index fc7daf5..28992db 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -81,11 +81,3 @@ optimized away by the compiler.
 
 Thanks,
 Alex.
-
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diff --git a/N1/2.hdr b/N1/2.hdr
new file mode 100644
index 0000000..6700619
--- /dev/null
+++ b/N1/2.hdr
@@ -0,0 +1,5 @@
+Content-Type: text/x-patch;
+	name="0001-WIP-no-dma-api-for-coherent-gpuobjs.patch"
+Content-Transfer-Encoding: 7bit
+Content-Disposition: attachment;
+	filename="0001-WIP-no-dma-api-for-coherent-gpuobjs.patch"
diff --git a/N1/2.txt b/N1/2.txt
new file mode 100644
index 0000000..19a5668
--- /dev/null
+++ b/N1/2.txt
@@ -0,0 +1,132 @@
+>From 6199967b4f690e5ca7f404ebb9d1d8840024b5b7 Mon Sep 17 00:00:00 2001
+From: Alexandre Courbot <acourbot@nvidia.com>
+Date: Thu, 3 Mar 2016 12:49:28 +0900
+Subject: [PATCH] WIP: no dma api for coherent gpuobjs
+X-NVConfidentiality: public
+
+---
+ drivers/gpu/drm/nouveau/nouveau_bo.c | 61 +++---------------------------------
+ 1 file changed, 5 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
+index db2a81461e0f..1112209ca871 100644
+--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
++++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
+@@ -424,13 +424,7 @@ nouveau_bo_map(struct nouveau_bo *nvbo)
+ 	if (ret)
+ 		return ret;
+ 
+-	/*
+-	 * TTM buffers allocated using the DMA API already have a mapping, let's
+-	 * use it instead.
+-	 */
+-	if (!nvbo->force_coherent)
+-		ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,
+-				  &nvbo->kmap);
++	ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
+ 
+ 	ttm_bo_unreserve(&nvbo->bo);
+ 	return ret;
+@@ -442,12 +436,7 @@ nouveau_bo_unmap(struct nouveau_bo *nvbo)
+ 	if (!nvbo)
+ 		return;
+ 
+-	/*
+-	 * TTM buffers allocated using the DMA API already had a coherent
+-	 * mapping which we used, no need to unmap.
+-	 */
+-	if (!nvbo->force_coherent)
+-		ttm_bo_kunmap(&nvbo->kmap);
++	ttm_bo_kunmap(&nvbo->kmap);
+ }
+ 
+ void
+@@ -514,35 +503,13 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
+ 	return 0;
+ }
+ 
+-static inline void *
+-_nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
+-{
+-	struct ttm_dma_tt *dma_tt;
+-	u8 *m = mem;
+-
+-	index *= sz;
+-
+-	if (m) {
+-		/* kmap'd address, return the corresponding offset */
+-		m += index;
+-	} else {
+-		/* DMA-API mapping, lookup the right address */
+-		dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;
+-		m = dma_tt->cpu_address[index / PAGE_SIZE];
+-		m += index % PAGE_SIZE;
+-	}
+-
+-	return m;
+-}
+-#define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
+-
+ void
+ nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
+ {
+ 	bool is_iomem;
+ 	u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
+ 
+-	mem = nouveau_bo_mem_index(nvbo, index, mem);
++	mem += index;
+ 
+ 	if (is_iomem)
+ 		iowrite16_native(val, (void __force __iomem *)mem);
+@@ -556,7 +523,7 @@ nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
+ 	bool is_iomem;
+ 	u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
+ 
+-	mem = nouveau_bo_mem_index(nvbo, index, mem);
++	mem += index;
+ 
+ 	if (is_iomem)
+ 		return ioread32_native((void __force __iomem *)mem);
+@@ -570,7 +537,7 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
+ 	bool is_iomem;
+ 	u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
+ 
+-	mem = nouveau_bo_mem_index(nvbo, index, mem);
++	mem += index;
+ 
+ 	if (is_iomem)
+ 		iowrite32_native(val, (void __force __iomem *)mem);
+@@ -1496,14 +1463,6 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm)
+ 	dev = drm->dev;
+ 	pdev = device->dev;
+ 
+-	/*
+-	 * Objects matching this condition have been marked as force_coherent,
+-	 * so use the DMA API for them.
+-	 */
+-	if (!nvxx_device(&drm->device)->func->cpu_coherent &&
+-	    ttm->caching_state == tt_uncached)
+-		return ttm_dma_populate(ttm_dma, dev->dev);
+-
+ #if IS_ENABLED(CONFIG_AGP)
+ 	if (drm->agp.bridge) {
+ 		return ttm_agp_tt_populate(ttm);
+@@ -1561,16 +1520,6 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
+ 	dev = drm->dev;
+ 	pdev = device->dev;
+ 
+-	/*
+-	 * Objects matching this condition have been marked as force_coherent,
+-	 * so use the DMA API for them.
+-	 */
+-	if (!nvxx_device(&drm->device)->func->cpu_coherent &&
+-	    ttm->caching_state == tt_uncached) {
+-		ttm_dma_unpopulate(ttm_dma, dev->dev);
+-		return;
+-	}
+-
+ #if IS_ENABLED(CONFIG_AGP)
+ 	if (drm->agp.bridge) {
+ 		ttm_agp_tt_unpopulate(ttm);
+-- 
+2.8.0
diff --git a/N1/3.hdr b/N1/3.hdr
new file mode 100644
index 0000000..5216513
--- /dev/null
+++ b/N1/3.hdr
@@ -0,0 +1,4 @@
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: base64
+Content-Disposition: inline
diff --git a/N1/3.txt b/N1/3.txt
new file mode 100644
index 0000000..3b3a377
--- /dev/null
+++ b/N1/3.txt
@@ -0,0 +1,4 @@
+_______________________________________________
+dri-devel mailing list
+dri-devel@lists.freedesktop.org
+https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/a/content_digest b/N1/content_digest
index 4b8c0a6..e88cc41 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,11 +1,15 @@
  "ref\057064992.1060509@arm.com\0"
  "ref\0570737F5.30105@nvidia.com\0"
  "ref\05707FC9F.50905@arm.com\0"
- "From\0acourbot@nvidia.com (Alexandre Courbot)\0"
- "Subject\0Nouveau crashes in 4.6-rc on arm64\0"
+ "From\0Alexandre Courbot <acourbot@nvidia.com>\0"
+ "Subject\0Re: Nouveau crashes in 4.6-rc on arm64\0"
  "Date\0Mon, 11 Apr 2016 16:22:28 +0900\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
- "\00:1\0"
+ "To\0Robin Murphy <robin.murphy@arm.com>"
+  dri-devel@lists.freedesktop.org
+  linux-arm-kernel@lists.infradead.org
+ " linux-kernel@vger.kernel.org\0"
+ "Cc\0bskeggs@redhat.com\0"
+ "\01:1\0"
  "b\0"
  "Hi Robin,\n"
  "\n"
@@ -89,14 +93,147 @@
  "optimized away by the compiler.\n"
  "\n"
  "Thanks,\n"
- "Alex.\n"
+ Alex.
+ "\01:2\0"
+ "fn\00001-WIP-no-dma-api-for-coherent-gpuobjs.patch\0"
+ "b\0"
+ ">From 6199967b4f690e5ca7f404ebb9d1d8840024b5b7 Mon Sep 17 00:00:00 2001\n"
+ "From: Alexandre Courbot <acourbot@nvidia.com>\n"
+ "Date: Thu, 3 Mar 2016 12:49:28 +0900\n"
+ "Subject: [PATCH] WIP: no dma api for coherent gpuobjs\n"
+ "X-NVConfidentiality: public\n"
+ "\n"
+ "---\n"
+ " drivers/gpu/drm/nouveau/nouveau_bo.c | 61 +++---------------------------------\n"
+ " 1 file changed, 5 insertions(+), 56 deletions(-)\n"
  "\n"
- "-------------- next part --------------\n"
- "A non-text attachment was scrubbed...\n"
- "Name: 0001-WIP-no-dma-api-for-coherent-gpuobjs.patch\n"
- "Type: text/x-patch\n"
- "Size: 3801 bytes\n"
- "Desc: not available\n"
- URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160411/46428d08/attachment.bin>
+ "diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c\n"
+ "index db2a81461e0f..1112209ca871 100644\n"
+ "--- a/drivers/gpu/drm/nouveau/nouveau_bo.c\n"
+ "+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c\n"
+ "@@ -424,13 +424,7 @@ nouveau_bo_map(struct nouveau_bo *nvbo)\n"
+ " \tif (ret)\n"
+ " \t\treturn ret;\n"
+ " \n"
+ "-\t/*\n"
+ "-\t * TTM buffers allocated using the DMA API already have a mapping, let's\n"
+ "-\t * use it instead.\n"
+ "-\t */\n"
+ "-\tif (!nvbo->force_coherent)\n"
+ "-\t\tret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,\n"
+ "-\t\t\t\t  &nvbo->kmap);\n"
+ "+\tret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);\n"
+ " \n"
+ " \tttm_bo_unreserve(&nvbo->bo);\n"
+ " \treturn ret;\n"
+ "@@ -442,12 +436,7 @@ nouveau_bo_unmap(struct nouveau_bo *nvbo)\n"
+ " \tif (!nvbo)\n"
+ " \t\treturn;\n"
+ " \n"
+ "-\t/*\n"
+ "-\t * TTM buffers allocated using the DMA API already had a coherent\n"
+ "-\t * mapping which we used, no need to unmap.\n"
+ "-\t */\n"
+ "-\tif (!nvbo->force_coherent)\n"
+ "-\t\tttm_bo_kunmap(&nvbo->kmap);\n"
+ "+\tttm_bo_kunmap(&nvbo->kmap);\n"
+ " }\n"
+ " \n"
+ " void\n"
+ "@@ -514,35 +503,13 @@ nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,\n"
+ " \treturn 0;\n"
+ " }\n"
+ " \n"
+ "-static inline void *\n"
+ "-_nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)\n"
+ "-{\n"
+ "-\tstruct ttm_dma_tt *dma_tt;\n"
+ "-\tu8 *m = mem;\n"
+ "-\n"
+ "-\tindex *= sz;\n"
+ "-\n"
+ "-\tif (m) {\n"
+ "-\t\t/* kmap'd address, return the corresponding offset */\n"
+ "-\t\tm += index;\n"
+ "-\t} else {\n"
+ "-\t\t/* DMA-API mapping, lookup the right address */\n"
+ "-\t\tdma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;\n"
+ "-\t\tm = dma_tt->cpu_address[index / PAGE_SIZE];\n"
+ "-\t\tm += index % PAGE_SIZE;\n"
+ "-\t}\n"
+ "-\n"
+ "-\treturn m;\n"
+ "-}\n"
+ "-#define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))\n"
+ "-\n"
+ " void\n"
+ " nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)\n"
+ " {\n"
+ " \tbool is_iomem;\n"
+ " \tu16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);\n"
+ " \n"
+ "-\tmem = nouveau_bo_mem_index(nvbo, index, mem);\n"
+ "+\tmem += index;\n"
+ " \n"
+ " \tif (is_iomem)\n"
+ " \t\tiowrite16_native(val, (void __force __iomem *)mem);\n"
+ "@@ -556,7 +523,7 @@ nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)\n"
+ " \tbool is_iomem;\n"
+ " \tu32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);\n"
+ " \n"
+ "-\tmem = nouveau_bo_mem_index(nvbo, index, mem);\n"
+ "+\tmem += index;\n"
+ " \n"
+ " \tif (is_iomem)\n"
+ " \t\treturn ioread32_native((void __force __iomem *)mem);\n"
+ "@@ -570,7 +537,7 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)\n"
+ " \tbool is_iomem;\n"
+ " \tu32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);\n"
+ " \n"
+ "-\tmem = nouveau_bo_mem_index(nvbo, index, mem);\n"
+ "+\tmem += index;\n"
+ " \n"
+ " \tif (is_iomem)\n"
+ " \t\tiowrite32_native(val, (void __force __iomem *)mem);\n"
+ "@@ -1496,14 +1463,6 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm)\n"
+ " \tdev = drm->dev;\n"
+ " \tpdev = device->dev;\n"
+ " \n"
+ "-\t/*\n"
+ "-\t * Objects matching this condition have been marked as force_coherent,\n"
+ "-\t * so use the DMA API for them.\n"
+ "-\t */\n"
+ "-\tif (!nvxx_device(&drm->device)->func->cpu_coherent &&\n"
+ "-\t    ttm->caching_state == tt_uncached)\n"
+ "-\t\treturn ttm_dma_populate(ttm_dma, dev->dev);\n"
+ "-\n"
+ " #if IS_ENABLED(CONFIG_AGP)\n"
+ " \tif (drm->agp.bridge) {\n"
+ " \t\treturn ttm_agp_tt_populate(ttm);\n"
+ "@@ -1561,16 +1520,6 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)\n"
+ " \tdev = drm->dev;\n"
+ " \tpdev = device->dev;\n"
+ " \n"
+ "-\t/*\n"
+ "-\t * Objects matching this condition have been marked as force_coherent,\n"
+ "-\t * so use the DMA API for them.\n"
+ "-\t */\n"
+ "-\tif (!nvxx_device(&drm->device)->func->cpu_coherent &&\n"
+ "-\t    ttm->caching_state == tt_uncached) {\n"
+ "-\t\tttm_dma_unpopulate(ttm_dma, dev->dev);\n"
+ "-\t\treturn;\n"
+ "-\t}\n"
+ "-\n"
+ " #if IS_ENABLED(CONFIG_AGP)\n"
+ " \tif (drm->agp.bridge) {\n"
+ " \t\tttm_agp_tt_unpopulate(ttm);\n"
+ "-- \n"
+ 2.8.0
+ "\01:3\0"
+ "b\0"
+ "_______________________________________________\n"
+ "dri-devel mailing list\n"
+ "dri-devel@lists.freedesktop.org\n"
+ https://lists.freedesktop.org/mailman/listinfo/dri-devel
 
-efc6da3e200f330b1889d3ae4061580bd08731892e6afe7815cccba1b1eb0ba0
+9f48bf60a58de2fae9efe4400c73320035b07dfc648e4ec7a848fbdefeb0cf90
